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Datasheet SY100S834 Equivalent ( PDF ) |
| N.º | Número de pieza | Descripción | Fabricantes | |
| 4 | SY100S834 | Clock Generation Chip SY100S834/SY100S834L
(÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) Clock Generation Chip Precision Edge®
General Description
The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchrono |
 Micrel Semiconductor |
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| 3 | SY100S834 | Pecl Clock Generation (÷1, ÷2, ÷4) OR (÷2, ÷4, ÷8) CLOCK GENERATION CHIP
ClockWorks™ SY100S834 SY100S834L FINAL
FEATURES
s s s s s s 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75KΩ input pull-down resistors Available in 16-p |
Micrel Semiconductor |
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| 2 | SY100S834L | Clock Generation Chip SY100S834/SY100S834L
(÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) Clock Generation Chip Precision Edge®
General Description
The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchrono |
Micrel Semiconductor |
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| 1 | SY100S834L | Pecl Clock Generation (÷1, ÷2, ÷4) OR (÷2, ÷4, ÷8) CLOCK GENERATION CHIP
ClockWorks™ SY100S834 SY100S834L FINAL
FEATURES
s s s s s s 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75KΩ input pull-down resistors Available in 16-p |
Micrel Semiconductor |
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