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DM74 Price ( Datasheet, Hoja de datos )

N.º Número de pieza Descripción Fabricantes PDF
790 DM74   

Hex Inverters with Schmitt Trigger Inputs


54LS14 DM74LS14 Hex Inverters with Schmitt Trigger Inputs June 1989 54LS14 DM74LS14 Hex Inverters with Schmitt Trigger Inputs General Description This device contains six independent gates each of which performs the logic INVERT function Each input has hysteresis which increases the noise immunity and transforms a slowly changing input signal to a fast changing jitter free output Connection Diagram Dual-In-Line Package TL F 6353 – 1 Order Number 54LS14DMQB 54LS14FMQB 54LS14LMQB DM74LS14M or DM74LS14N See NS Package Number E20A J14A M14A N14A or W14B Function Table YeA Input A L H H e High Logic Level L e Low Logic Level Output Y H L
National Semiconductor
National Semiconductor
datasheet DM74 pdf
789 DM7400   

Quad 2-Input NAND Gates


5400 DM5400 DM7400 Quad 2-Input NAND Gates June 1989 5400 DM5400 DM7400 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function Features Y Alternate Military Aerospace device (5400) is available Contact a National Semiconductor Sales Office Distributor for specifications Connection Diagram Dual-In-Line Package TL F 6613 – 1 Order Number 5400DMQB 5400FMQB DM5400J DM5400W or DM7400N See NS Package Number J14A N14A or W14B Function Table Y e AB Inputs Output AB Y LL LH HL HH H H H L H e High Logic Level L e Low Logic Level C1995 National Semiconduct
National Semiconductor
National Semiconductor
datasheet DM7400 pdf
788 DM7400   

Quad 2-Input NAND Gates


DM7400 Quad 2-Input NAND Gates September 1986 Revised February 2000 DM7400 Quad 2-Input NAND Gates General Description This device contains four independent gates each of which performs the logic NAND function. Ordering Code: Order Number DM7400M DM7400N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Y = AB Inputs A L L H H H = HIGH Logic Level L = LOW L
Fairchild Semiconductor
Fairchild Semiconductor
datasheet DM7400 pdf
787 DM7401   

DM5401 DM7401 Quad 2-Input NAND Gates with Open-Collector Outputs (Rev. A)


Texas Instruments
Texas Instruments
datasheet DM7401 pdf
786 DM7401   

Quad 2-Input NAND Gates with Open-Collector Outputs


DM5401 DM7401 Quad 2-Input NAND Gates with Open-Collector Outputs June 1989 DM5401 DM7401 Quad 2-Input NAND Gates with Open-Collector Outputs General Description This device contains four independent gates each of which performs the logic NAND function The open-collector outputs require external pull-up resistors for proper logical operation Pull-Up Resistor Equations RMAX e VCC (Min) b VOH N1 (IOH) a N2 (IIH) VCC (Max) b VOL RMIN e IOL b N3 (IIL) Where N1 (IOH) e total maximum output high current for all outputs tied to pull-up resistor N2 (IIH) e total maximum input high current for all inputs tied to pull-up resistor N3 (IIL) e total m
National Semiconductor
National Semiconductor
datasheet DM7401 pdf
785 DM7402   

Quad 2-Input NOR Gates


5402 DM5402 DM7402 Quad 2-Input NOR Gates June 1989 5402 DM5402 DM7402 Quad 2-Input NOR Gates General Description This device contains four independent gates each of which performs the logic NOR function Features Y Alternate Military Areospace device (5402) is available Contact a National Semiconductor Sales Office Distributor for specifications Connection Diagram Dual-In-Line Package TL F 6492 – 1 Order Number 5402DMQB 5402FMQB DM5402J DM5402W or DM7402N See NS Package Number J14A N14A or W14B Function Table YeAaB Inputs Output AB Y LL LH HL HH H L L L H e High Logic Level L e Low Logic Level C1995 National Semiconductor C
National Semiconductor
National Semiconductor
datasheet DM7402 pdf
784 DM7402   

Quad 2-Input NOR Gates


DM7402 Quad 2-Input NOR Gates August 1986 Revised February 2000 DM7402 Quad 2-Input NOR Gates General Description This device contains four independent gates each of which performs the logic NOR function. Ordering Code: Order Number DM7402N Package Number N14A Package Description 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram Function Table Y= A+B Inputs A L L H H H = HIGH Logic Level L = LOW Logic Level Output B L H L H Y H L L L © 2000 Fairchild Semiconductor Corporation DS006492 www.fairchildsemi.com DM7402 Absolute Maximum Ratings(Note 1) Supply Voltage Input Voltage Operating Free Air
Fairchild Semiconductor
Fairchild Semiconductor
datasheet DM7402 pdf
783 DM7403   

DM5403 DM7403 Quad 2-Input NAND Gates with Open-Collector Outputs (Rev. A)


Texas Instruments
Texas Instruments
datasheet DM7403 pdf
782 DM7403   

Quad 2-Input NAND Gates with Open-Collector Outputs


DM7403 Quad 2-Input NAND Gates with Open-Collector Outputs August 1986 Revised February 2000 DM7403 Quad 2-Input NAND Gates with Open-Collector Outputs General Description This device contains four independent gates each of which performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation. Pull-Up Resistor Equations Where: N1 (IOH) = total maximum output high current for all outputs tied to pull-up resistor N2 (IIH) = total maximum input high current for all inputs tied to pull-up resistor N3 (IIL) = total maximum input low current for all inputs tied to pull-up resistor O
Fairchild Semiconductor
Fairchild Semiconductor
datasheet DM7403 pdf
781 DM7403N   

Quad 2-Input NAND Gates with Open-Collector Outputs


DM7403 Quad 2-Input NAND Gates with Open-Collector Outputs August 1986 Revised February 2000 DM7403 Quad 2-Input NAND Gates with Open-Collector Outputs General Description This device contains four independent gates each of which performs the logic NAND function. The open-collector outputs require external pull-up resistors for proper logical operation. Pull-Up Resistor Equations Where: N1 (IOH) = total maximum output high current for all outputs tied to pull-up resistor N2 (IIH) = total maximum input high current for all inputs tied to pull-up resistor N3 (IIL) = total maximum input low current for all inputs tied to pull-up resistor O
Fairchild Semiconductor
Fairchild Semiconductor
datasheet DM7403N pdf


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