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PDF 24C02 Data sheet ( Hoja de datos )
| Número de pieza | 24C02 | |
| Descripción | Two-Wire Serial EEPROM | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 24C02 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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24C02/24C04
Preliminary datasheet
Features
Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
Operating Ambient Temperature: -40°C to
+85°C
Internally Organized 256 X 8 (2K), 512 X 8
(4K)
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise
Suppression
Bidirectional Data Transfer Protocol
1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V)
Two-Wire Serial EEPROM
2K (256 X 8)/4K (512 X 8)
Compatibility
Write Protect Pin for Hardware Data Protection
8-byte Page (2K), 16-byte Page (4K) Write
Modes
Partial Page Writes Allowed
Self-timed Write Cycle (5 ms max)
High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
8-lead PDIP, 8-lead JEDEC SOIC and 8-lead
TSSOP Packages
General Description
The 24C02 / 24C04 provides 2048/4096 bits of
serial electrically erasable and programmable
read-only memory (EEPROM) organized as
256/512 words of 8 bits each The device is
optimized for use in many industrial and
commercial applications where low-power and
low-voltage operation are essential. The 24C02 /
24C04 is available in space-saving 8-lead PDIP,
8-lead JEDEC SOIC, and 8-lead TSSOP packages
and is accessed via a Two-wire serial interface. In
addition, the 24C02 / 24C04 is available in 1.8V
(1.8V to 5.5V) version.
Pin Configuration
1/15
MRD
1 page  
Figure 2. Start and Stop Definition
Figure 3. Output Acknowledge
24C02/24C04
3. Device Addressing
The 2K and 4K EEPROM devices all require an 8-bit device address word following a start condition to enable
the chip for a read or write operation (see to Figure 4 on page 4).
The device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits as
shown. This is common to all the Serial EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to
their corresponding hardwired input pins.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address
bit. The two device address bits must compare to their corresponding hardwired input pins. The A0 pin is no
connect.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this
bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the chip will
return to a standby state.
5/15 MRD
5 Page 
Bus Timing
Figure 10. SCL: Serial Clock, SDA: Serial Data I/O
24C02/24C04
Write Cycle Timing
Figure 11. SCL: Serial Clock, SDA: Serial Data I/O
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of
the internal clear/write cycle.
11/15
MRD
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet 24C02.PDF ] | |
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