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PDF dsPIC33EP128MC506 Data sheet ( Hoja de datos )

Número de pieza dsPIC33EP128MC506
Descripción 16-Bit Microcontrollers and Digital Signal Controllers
Fabricantes Microchip 
Logotipo Microchip Logotipo



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dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X
16-Bit Microcontrollers and Digital Signal Controllers
with High-Speed PWM, Op Amps and Advanced Analog
Operating Conditions
• 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS
• 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS
Core: 16-Bit dsPIC33E/PIC24E CPU
• Code Efficient (C and Assembly) Architecture
• Two 40-Bit-Wide Accumulators
• Single Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle, Mixed-Sign MUL plus Hardware Divide
• 32-Bit Multiply Support
Clock Management
• 1.0% Internal Oscillator
• Programmable PLLs and Oscillator Clock Sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer (WDT)
• Fast Wake-up and Start-up
Power Management
• Low-Power Management modes (Sleep, Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
• 0.6 mA/MHz Dynamic Current (typical)
• 30 µA IPD Current (typical)
High-Speed PWM
• Up to Three PWM Pairs with Independent Timing
• Dead Time for Rising and Falling Edges
• 7.14 ns PWM Resolution
• PWM Support for:
- DC/DC, AC/DC, Inverters, PFC, Lighting
- BLDC, PMSM, ACIM, SRM
• Programmable Fault Inputs
• Flexible Trigger Configurations for ADC Conversions
Advanced Analog Features
• ADC module:
- Configurable as 10-bit, 1.1 Msps with four S&H or
12-bit, 500 ksps with one S&H
- Six analog inputs on 28-pin devices and up to
16 analog inputs on 64-pin devices
• Flexible and Independent ADC Trigger Sources
• Up to Three Op Amp/Comparators with
Direct Connection to the ADC module:
- Additional dedicated comparator
- Programmable references with 32 voltage points
• Charge Time Measurement Unit (CTMU):
- Supports mTouch™ capacitive touch sensing
- Provides high-resolution time measurement (1 ns)
- On-chip temperature measurement
Timers/Output Compare/Input Capture
• 12 General Purpose Timers:
- Five 16-bit and up to two 32-bit timers/counters
- Four Output Compare (OC) modules, configurable
as timers/counters
- PTG module with two configurable timers/counters
- 32-bit Quadrature Encoder Interface (QEI) module,
configurable as a timer/counter
• Four Input Capture (IC) modules
• Peripheral Pin Select (PPS) to allow Function Remap
• Peripheral Trigger Generator (PTG) for Scheduling
Complex Sequences
Communication Interfaces
• Two UART modules (17.5 Mbps):
- With support for LIN/J2602 protocols and IrDA®
• Two 4-Wire SPI modules (15 Mbps)
• ECAN™ module (1 Mbaud) CAN 2.0B Support
• Two I2C™ modules (up to 1 Mbaud) with SMBus
Support
• PPS to allow Function Remap
• Programmable Cyclic Redundancy Check (CRC)
Direct Memory Access (DMA)
• 4-Channel DMA with User-Selectable Priority Arbitration
• UART, SPI, ADC, ECAN, IC, OC and Timers
Input/Output
• Sink/Source 12 mA or 6 mA, Pin-Specific for
Standard VOH/VOL, up to 22 or 14 mA, respectively
for Non-Standard VOH1
• 5V Tolerant Pins
• Peripheral Pin Select (PPS) to allow Digital Function
Remapping
• Selectable Open-Drain, Pull-ups and Pull-Downs
• Up to 5 mA Overvoltage Clamp Current
• Change Notification Interrupts on All I/O Pins
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1, -40°C to +125°C) Planned
• AEC-Q100 REVG (Grade 0, -40°C to +150°C) Planned
• Class B Safety Library, IEC 60730
Debugger Development Support
• In-Circuit and In-Application Programming
• Two Program and Two Complex Data Breakpoints
• IEEE 1149.2 Compatible (JTAG) Boundary Scan
• Trace and Run-Time Watch
2011-2013 Microchip Technology Inc.
DS70000657H-page 1

1 page




dsPIC33EP128MC506 pdf
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams
28-Pin SPDIP/SOIC/SSOP(1,2)
= Pins are up to 5V tolerant
MCLR
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
VSS
OSC1/CLKI/RA2
OSC2/CLKO/RA3
RP36/RB4
CVREF2O/RP20/T1CK/RA4
VDD
PGED2/ASDA2/RP37/RB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 AVDD
27 AVSS
26 RPI47/T5CK/RB15
25 RPI46/T3CK/RB14
24 RPI45/CTPLS/RB13
23 RPI44/RB12
22 TDI/RP43/RB11
21 TDO/RP42/RB10
20 VCAP
19 VSS
18 TMS/ASDA1/SDI1/RP41/RB9(3)
17 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
16 SCK1/RP39/INT0/RB7
15 PGEC2/ASCL2/RP38/RB6
MCLR
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
VSS
OSC1/CLKI/RA2
OSC2/CLKO/RA3
FLT32/RP36/RB4
CVREF2O/RP20/T1CK/RA4
VDD
PGED2/ASDA2/RP37/RB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 AVDD
27 AVSS
26 RPI47/PWM1L/T5CK/RB15
25 RPI46/PWM1H/T3CK/RB14
24 RPI45/PWM2L/CTPLS/RB13
23 RPI44/PWM2H/RB12
22 TDI/RP43/PWM3L/RB11
21 TDO/RP42/PWM3H/RB10
20 VCAP
19 VSS
18 TMS/ASDA1/SDI1/RP41/RB9(3)
17 TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
16 SCK1/RP39/INT0/RB7
15 PGEC2/ASCL2/RP38/RB6
Note 1:
2:
3:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
2011-2013 Microchip Technology Inc.
DS70000657H-page 5

5 Page





dsPIC33EP128MC506 arduino
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
Pin Diagrams (Continued)
44-Pin TQFP(1,2)
= Pins are up to 5V tolerant
TMS/ASDA1/RP41/RB9(3)
RP54/RC6
RP55/RC7
RP56/RC8
RP57/RC9
VSS
VCAP
RP42/PWM3H/RB10
RP43/PWM3L/RB11
RPI44/PWM2H/RB12
RPI45/PWM2L/CTPLS/RB13
1
2
3
4
5
6
7
8
9
10
11
dsPIC33EPXXXMC204/504
PIC24EPXXXMC204
33 FLT32/SCL2/RP36/RB4
32 SDA2/RPI24/RA8
31 OSC2/CLKO/RA3
30 OSC1/CLKI/RA2
29 VSS
28 VDD
27 AN8/C3IN1+/U1RTS/BCLK1/FLT3/RC2
26 AN7/C3IN1-/C4IN1-/RC1
25 AN6/OA3OUT/C4IN1+/OCFB/RC0
24 PGED1/AN5/C1IN1-/RP35/RB3
23 PGEC1/AN4/C1IN1+/RPI34/RB2
Note 1:
2:
3:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4
“Peripheral Pin Select (PPS)” for available peripherals and for information on limitations.
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O
Ports” for more information.
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the
JTAGEN bit field in Table 27-2.
2011-2013 Microchip Technology Inc.
DS70000657H-page 11

11 Page







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