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PDF L9822N Data sheet ( Hoja de datos )
| Número de pieza | L9822N | |
| Descripción | OCTAL SERIAL SOLENOID DRIVER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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L9822N
OCTAL SERIAL SOLENOID DRIVER
. EIGHT LOW RDSon DMOS OUTPUTS
(0.5Ω AT IO = 1A @ 25°C VCC = 5V± 5%)
. 8 BIT SERIAL INPUT DATA (SPI)
. 8 BIT SERIAL DIAGNOSTIC OUTPUT FOR
OVERLOADAND OPENCIRCUIT CONDITIONS
. OUTPUT SHORT CIRCUIT PROTECTION
. CHIPENABLESELECTFUNCTION (active low)
. INTERNAL 35V CLAMPING FOR EACH OUT-
PUT
. CASCADABLE WITH ANOTHER OCTAL
DRIVER
. LOW QUIESCENT CURRENT (10mA MAX.)
. PACKAGE Power SO20
DESCRIPTION
The L9822N is an octal low side solenoid driver
rea lized in Multipower-BCD technology particularly
suited for driving lamps, relays and solenoids in au-
MULTIPOWER BCD TECHNOLOGY
PowerSO20
ORDERING NUMBER: L9822N
tomotive environment. The DMOS outpts L9822N
has a very low power consumption.
Data is transmitted serially to the device using the
Serial Peripheral Interface (SPI) protocol.
The L9822N features the outputsstatus monitoring
function.
BLOCK DIAGRAM
October 1997
1/9
1 page  
L9822N
FUNCTIONAL DESCRIPTION
The L9822NDMOS output is a low operating power
device featu-ring, eight 1Ω RDSON DMOS drivers
with transient protection circuits in output stages.
Each channel is independentlycontrolled by an out-
put latch and a common RESET line which disables
all eight outputs. The driver has low saturation and
shortcircuit protectionand candrive inductiveandre-
sistive loads such as solenoids, lamps and relais.
Datais transmittedtothe deviceseriallyusingtheSe-
rialPeripheral Interface(SPI) protocol. The circuit re-
ceives 8 bit serial data by means of the serial input
(SI) which is stored in an internal register to control
the output drivers. The serial output (SO) provides 8
bit of diagnostic data representing the voltage level
at the driver output. This allows the microprocessor
to diagnosethe condition of the output drivers.
The output saturation voltage is monitored by a
comparator for an out of saturation condition and is
able to unlatch the particular driver through the fault
reset line. This circuit is also cascadable with ano-
ther octal driver in order to jam 8 bit multiple data.
The device is selected when the chip enable (CE)
line is low.
Additionally the (SO) is placed in a tri-state mode
when the device is deselected. The negative edge
of the (CE) transfers the voltage level of the drivers
to the shift registerand the positive edge of the (CE)
latchesthe new datafrom the shift registerto the dri-
vers. When CE is Low, data bit contained into the
shift register is transferred to SO output at every
SCLK positive transition while data bit present at SI
input is latched into the shift register on every SCLK
negative transition.
Internal Blocks Description
The internal architecture of the device is based on
the three internal major blocks : the octal shift regi-
ster for talking to the SPI bus, the octal latch for hol-
ding control bits written into the device and the octal
load driver array.
Shift Register
The shift register has both serial and parallel inputs
and serial and parallel outputs. The serial input ac-
cepts data from the SPI bus and the serial output si-
multaneously sends data into the SPI bus. The
parallel outputs are latched into the parallel latch in-
side the L9822N at the end of a data transfer. The
parallel inputs jam diagnostic data into the shift re-
gister at the beginning of a data transfer cycle.
Parallel Latch
The parallel latch holds the input data from the shift
register. This data then actuates the output stages.
Individual registers in the latch may be cleared by
fault conditions in order to protect the overloaded
output stages. The entire latch may also be cleared
by the RESET signal.
Output Stages
The output stagesprovide an active low drive signal
suitable for 0.75A continuous loads. The outputs
have internal zeners set to 36 volts to clamp induc-
tive transients at turn-off. Each output also has a
voltagecomparatorobservingthe outputnode.If the
voltage exceeds 1.8V on an ON output pin, a fault
condition is assumed and the latch driving this par-
ticular stage is reset, turning the output OFF to pro-
tect it. The timing of this action is described below.
These comparators also provide diagnostic feed-
back data to the shift register. Additionally, the com-
parators contain an internal pulldown current which
will cause the cell to indicate a low output voltage if
the output is programmed OFF and the output pin
is open circuited.
TIMING DATA TRANSFER
Figure #2 shows the overall timing diagram from a
byte transfer to and from the L9822NSP using the
SPI bus.
CE High to Low Transition
The action begins when the Chip Enable(CE) pin is
pulledlow. The tri-state Serial Output(SO)pin driver
will be enabledentire time that CE is low. At the fal-
ling edge of the CE pin, the diagnostic data from the
voltage comparatorsin the output stages will be lat-
ched into the shift register. If a particular output is
high, a logic one will be jammed into that bit in the
shift register. If the output is low, a logic zero will be
loadedthere. The most significant bit (07) shouldbe
presented at the Serial Input (SI) pin. A zero at this
pin will program an output ON, while a one will pro-
gram the output OFF.
SCLK Transitions
The Serial Clock (SCLK) pin should then be pulled
high. At thispoint the diagnostic bit from the most si-
gnificantoutput(07) will appearat the SO pin.A high
here indicates that the 07 pin is higher than 1.8V.
The SCLK pin shouldthen be toggledlow then high.
New SO data will appearfollowingevery rising edge
of SCLK and new SI data will be latched into the
L9822N shift register on the falling edges. An unli-
mitedamount ofdata may be shifted throughthe de-
vice shift register (into the SI pin and out the SO pin),
allowing the other SPI devices to be cascaded in a
daisy chain with the L9822N.
5/9
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet L9822N.PDF ] | |
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