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PDF R5F117AC Data sheet ( Hoja de datos )

Número de pieza R5F117AC
Descripción MCU
Fabricantes Renesas 
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No Preview Available ! R5F117AC Hoja de datos, Descripción, Manual

RL78/I1D
RENESAS MCU
1. OUTLINE
1.1 Features
Ultra-low power consumption technology
• VDD = 1.6 V to 3.6 V
• HALT mode
• STOP mode
• SNOOZE mode
RL78 CPU core
• CISC architecture with 3-stage pipeline
• Minimum instruction execution time: Can be changed
from high speed (0.04167 s: @ 24 MHz operation with
high-speed on-chip oscillator) to ultra-low speed (66.6
s: @ 15 kHz operation with low-speed on-chip
oscillator clock)
• Multiply/divide/multiply & accumulate instructions are
supported.
• Address space: 1 MB
• General-purpose registers: (8-bit register 8) 4 banks
• On-chip RAM: 0.7 to 3 KB
Code flash memory
• Code flash memory: 8 to 32 KB
• Block size: 1 KB
• Prohibition of block erase and rewriting (security
function)
• On-chip debug function
• Self-programming (with boot swap function/flash shield
window function)
Data flash memory
• Data flash memory: 2 KB
• Back ground operation (BGO): Instructions can be
executed from the program memory while rewriting the
data flash memory.
• Number of rewrites: 1,000,000 times (TYP.)
• Voltage of rewrites: VDD = 1.8 to 3.6 V
High-speed on-chip oscillator
• Select from 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4
MHz, 3 MHz, 2 MHz, and 1 MHz
• High accuracy: ±1.0% (VDD = 1.8 to 3.6 V, TA = -20 to
+85°C)
Middle-speed on-chip oscillator
• Selectable from 4 MHz, 2 MHz, and 1 MHz.
Operating ambient temperature
• TA = -40 to +105°C (G: Industrial applications)
Power management and reset function
• On-chip power-on-reset (POR) circuit
• On-chip voltage detector (LVD) (Select interrupt and
reset from 12 levels)
R01DS0244EJ0200 Rev. 2.00
Jan 16, 2015
Datasheet
R01DS0244EJ0200
Rev. 2.00
Jan 16, 2015
Data transfer controller (DTC)
• Transfer modes: Normal transfer mode, repeat transfer
mode, block transfer mode
• Activation sources: Activated by interrupt sources.
• Chain transfer function
Event link controller (ELC)
• Event signals of 20 types can be linked to the specified
peripheral function.
Serial interfaces
• CSI: 2 channels
• UART: 1 channel
• I2C/simplified I2C: 2 channels
Timers
• 16-bit timer: 4 channels
• 12-bit interval timer: 1 channel
• 8-bit interval timer: 4 channels
• Real-time clock: 1 channel (calendar for 99 years, alarm
function, and clock correction function)
• Watchdog timer: 1 channel
A/D converter
• 8/12-bit resolution A/D converter (VDD = 1.6 to 3.6 V)
• Analog input: 6 to 17 channels
• Internal reference voltage (1.45 V) and temperature
sensor
Comparator
• 2 channels
• Operating modes: Comparator high-speed mode,
comparator low-speed mode, window mode
Operational amplifier
• 4 channels
I/O ports
• I/O port: 14 to 42 (N-ch open drain I/O [withstand
voltage of 6 V]: 4, N-ch open drain I/O [VDD withstand
voltage]: 3 to 7)
• Can be set to N-ch open drain, TTL input buffer, and on-
chip pull-up resistor
• Different potential interface: Can connect to a 1.8/2.5 V
device
• On-chip key interrupt function
• On-chip clock output/buzzer output controller
Others
• On-chip BCD (binary-coded decimal) correction circuit
• On-chip data operation circuit
Remark The functions mounted depend on the
product. See 1.6 Outline of Functions.
Page 1 of 99

1 page




R5F117AC pdf
RL78/I1D
1.3 Pin Configuration (Top View)
1.3.1 20-pin products
• 20-pin plastic LSSOP (4.4 6.5 mm, 0.65 mm pitch)
1. OUTLINE
P12/ANI2/AMP0+
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P55/SI00/RxD0/SDA00/INTP2/TOOLRXD
1
2
3
4
5
6
7
8
9
10
20 P13/ANI3/AMP0-
19 P14/ANI4/IVCMP0/AMP0O
18 AVSS
17 AVDD
16 P22/ANI11/AMP3+
15 P21/ANI12/AMP3-
14 P20/ANI13/IVCMP1/AMP3O
13 P31/TI01/TO00/PCLBUZ0/IVREF1
12 P30/SCK00/SCL00/TI00/TO01/IVREF0
11 P54/SO00/TxD0/INTP1/TOOLTXD
Caution 1. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Caution 2. Make AVSS pin the same potential as VSS pin.
Caution 3. Make AVDD pin the same potential as VDD pin.
Remark For pin identification, see 1.4 Pin Identification.
R01DS0244EJ0200 Rev. 2.00
Jan 16, 2015
Page 5 of 99

5 Page





R5F117AC arduino
RL78/I1D
1.4 Pin Identification
ANI0 to ANI13,
ANI16 to ANI18
AVDD
AVREFM
AVREFP
AVSS
EXCLK
EXCLKS
INTP0 to INTP6
IVCMP0, IVCMP1
IVREF0, IVREF1
KR0 to KR3
P00 to P04
P10 to P17
P20 to P25
P30 to P33
P40
P50 to P57
P60 to P63
P121 to P124
P130, P137
: Analog input
: Analog power supply
: A/D converter reference
potential (- side) input
: A/D converter reference
potential (+ side) input
: Analog ground
: External clock input
(main system clock)
: External clock input
(subsystem clock)
: External interrupt input
: Comparator input
: Comparator reference input
: Key return
: Port 0
: Port 1
: Port 2
: Port 3
: Port 4
: Port 5
: Port 6
: Port 12
: Port 13
1. OUTLINE
PCLBUZ0, PCLBUZ1
REGC
RESET
RTC1HZ
RxD0
SCK00, SCK01
SCL00, SCL01
SDA00, SDA01
SI00, SI01
SO00, SO01
SSI00
TI00 to TI03
TO00 to TO03
TOOL0
TOOLRXD, TOOLTXD
TxD0
VCOUT0, VCOUT1
AMP0+, AMP1+,
AMP2+, AMP3+
AMP0-, AMP1-,
AMP2-, AMP3-
AMP0O, AMP1O,
AMP2O, AMP3O
VDD
VSS
X1, X2
XT1, XT2
: Programmable clock output/buzzer
output
: Regulator capacitance
: Reset
: Real-time clock correction clock (1 Hz)
output
: Receive data
: Serial clock input/output
: Serial clock input/output
: Serial data input/output
: Serial data input
: Serial data output
: Serial interface chip select input
: Timer input
: Timer output
: Data input/output for tool
: Data input/output for external device
: Transmit data
: Comparator output
: Operational amplifier (+side) input
: Operational amplifier (-side) input
: Operational amplifier output
: Power supply
: Ground
: Crystal oscillator (main system clock)
: Crystal oscillator (subsystem clock)
R01DS0244EJ0200 Rev. 2.00
Jan 16, 2015
Page 11 of 99

11 Page







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