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PDF L9638D013TR Data sheet ( Hoja de datos )
| Número de pieza | L9638D013TR | |
| Descripción | LIN BUS TRANSCEIVER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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L9638
LIN BUS TRANSCEIVER
1 FEATURES
■ Single-wire transceiver for LIN-protocol
■ Transmission rate up to 20 kbaud
■ Operating power supply voltage range 6V ≤ Vs
≤ 26V (40V for transients)
■ Low quiescent current in sleep mode (typ.10µA)
■ Wake-up through LIN-bus, Enable input (from
µC CMOS compatible) or Wake-up input (edge
driven)
■ Wide input and output range -24V ≤ VLIN ≤ Vs
■ Integrated pull/down/up resistors for LIN, TxD,
RxD, EN, INH
■ Inhibit output with low resistance (<40Ω) versus
Vs and short circuit protection
■ CMOS compatible TxD, RxD Interface
■ EMI robustness optimised
■ Thermal shutdown and LIN short circuit
protection
Figure 1. Block Diagram
SO-8
Table 1. Order Codes
Part Number
L9638D
L9638D013TR
Package
SO-8
Tape & Reel
2 DESCRIPTION
The L9638 is a monolithic integrated circuit for
LIN-bus interface function between the protocol
handler in the controller and the physical bus in
automotive applications.
As well as it can be used in standard ISO 9141
systems.
VS
Int.5V
Internal
Voltage
Regulator
RxD
Glitch
Filter
VS_D
LIN
TxD
EN
WUP
Glitch
Filter
Control
Logic
Protection
VS_D
INH
GND
October 2004
Rev. 4
1/14
1 page  
L9638
Table 5. Electrical Characteristics (continued)
(VS = 6V to 26V; TJ = -40 to 150 °C unless otherwise specified)
Item Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
6.3 tWUPgs Remote wake-up delay time Transitioning on WUP
40 100 µs
7 Enable Input EN
7.1 VENLow Low level input voltage
7.2 VENHigh High level input voltage
7.3 REN EN pull down resistor
7.4 tgts Go to sleep delay time
7.5
tENgs
EN wake-up glitch
suppression time
VEN = VENlow
VEN = VENhigh
1.5 V
3.5 V
5 10 25 KΩ
40 100 µs
40 100 µs
8 AC Timing Parameters
8.1 D1 Duty Cycle 1
THRec(max) = 0.744 x VSUP;
THDom(max) = 0.581 x VSUP;
Vsup = 7.0 to 18V; tbit = 50µs;
D1 = tBus_rec(min)/2 x tBit
(CBUS; RBUS) 1nF; 1kΩ/6.8nF;
660Ω/10nF; 500Ω
0.396
8.2 D2 Duty Cycle 2
THRec(min) = 0.284 x VSUP;
THDom(min) = 0.422 x VSUP;
Vsup = 7.6 to 18V; tbit = 50µs;
D2 = tBus_rec(min)/2 x tBit
(CBUS; RBUS) 1nF; 1kΩ/6.8nF;
660Ω/10nF; 500Ω
0.581
8.3 D3 Duty Cycle 3
THRec(max) = 0.778 x VSUP;
THDom(max) = 0.616 x VSUP;
Vsup = 7.0 to 18V; tbit = 96µs;
D3 = tBus_rec(min)/2 x tBit
(CBUS; RBUS) 1nF; 1kΩ/6.8nF;
660Ω/10nF; 500Ω
0.417
8.4 D4 Duty Cycle 4
THRec(min) = 0.251 x VSUP;
THDom(min) = 0.389 x VSUP;
Vsup = 7.6 to 18V; tbit = 96µs;
D4 = tBus_rec(min)/2 x tBit
(CBUS; RBUS) 1nF; 1kΩ/6.8nF;
660Ω/10nF; 500Ω
0.591
9 Fault Conditions
9.1 ILIN_NO_GND LIN current with GND
disconnected
9.2 ILIN_NO_Vs LIN current with VS
grounded
Note: 1. Room temperature evaluated - no 100% tested
GND = Vs = 12V
0V< VLIM < 18V
(1)
V = GND, 0V < VLIN < 18V
(1)
-1
1 mA
100 µA
5/14
5 Page 
L9638
Figure 7. Typical Application Circuit
VBAT
VS
CS
RS RLIN
1
EN
VS 8
6
WD
3 RES
Vo 7
CTR
4 VCR
GND
VCW 5
CO
2 CTW
EXTERNAL
SWITCH
µCWD RXD
VCC
TXD
RES GND
EN
3
WUP
1
RXD
4
TXD
2
EN
VS 7
LIN 6
GND
5
INH 8
CLIN
LIN
BUS
Suggested Values
CS =100 nF
CTR = 1 nF
CTW = 47 nF
CO = 10 µF
CLIN_MASTER = 1 nF
CLIN_SLAVE = 220 pF
RS = 100 kΩ
RLIN = 1 kΩ
11/14
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