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PDF W9825G6JB Data sheet ( Hoja de datos )

Número de pieza W9825G6JB
Descripción 4M x 4-BANKS x 16-BITS SDRAM
Fabricantes Winbond 
Logotipo Winbond Logotipo



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No Preview Available ! W9825G6JB Hoja de datos, Descripción, Manual

W9825G6JB
4 M 4 BANKS 16 BITS SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. ORDER INFORMATION ............................................................................................................. 3
4. BALL CONFIGURATION ............................................................................................................ 4
5. BALL DESCRIPTION .................................................................................................................. 5
6. BLOCK DIAGRAM ...................................................................................................................... 6
7. FUNCTIONAL DESCRIPTION.................................................................................................... 7
7.1 Power Up and Initialization ............................................................................................. 7
7.2 Programming Mode Register.......................................................................................... 7
7.3 Bank Activate Command ................................................................................................ 7
7.4 Read and Write Access Modes ...................................................................................... 7
7.5 Burst Read Command .................................................................................................... 8
7.6 Burst Write Command .................................................................................................... 8
7.7 Read Interrupted by a Read ........................................................................................... 8
7.8 Read Interrupted by a Write............................................................................................ 8
7.9 Write Interrupted by a Write............................................................................................ 8
7.10 Write Interrupted by a Read............................................................................................ 8
7.11 Burst Stop Command ..................................................................................................... 9
7.12 Addressing Sequence of Sequential Mode .................................................................... 9
7.13 Addressing Sequence of Interleave Mode...................................................................... 9
7.14 Auto-precharge Command ........................................................................................... 10
7.15 Precharge Command.................................................................................................... 10
7.16 Self Refresh Command ................................................................................................ 10
7.17 Power Down Mode........................................................................................................ 11
7.18 No Operation Command ............................................................................................... 11
7.19 Deselect Command ...................................................................................................... 11
7.20 Clock Suspend Mode.................................................................................................... 11
8. OPERATION MODE ................................................................................................................. 12
9. ELECTRICAL CHARACTERISTICS ......................................................................................... 13
9.1 Absolute Maximum Ratings .......................................................................................... 13
9.2 Recommended DC Operating Conditions .................................................................... 13
9.3 Capacitance .................................................................................................................. 14
9.4 DC Characteristics ........................................................................................................ 14
9.5 AC Characteristics and Operating Condition ................................................................ 15
10. TIMING WAVEFORMS ............................................................................................................. 17
10.1 Command Input Timing ................................................................................................ 17
10.2 Read Timing.................................................................................................................. 18
10.3 Control Timing of Input/Output Data ............................................................................. 19
Publication Release Date: Jul. 17, 2014
- 1 - Revision: A05

1 page




W9825G6JB pdf
W9825G6JB
5. BALL DESCRIPTION
BALL LOCATION BALL NAME FUNCTION
DESCRIPTION
H7, H8, J8, J7, J3,
J2, H3, H2, H1,
G3, H9, G2, G1
A0A12
Address
Multiplexed pins for row and column address.
Row address: A0A12. Column address: A0A8.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
G7, G8
BS0, BS1
Bank Select
Select bank to activate during row address latch
time, or bank to read/write during address latch time.
A8, B9, B8, C9,
C8, D9, D8, E9,
E1, D2, D1, C2,
C1, B2, B1, A2
DQ0DQ15
Data
Input/ Output
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
G9 CS Chip Select command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
F8
RAS
Row Address
Strobe
the clock RAS , CAS and WE define the
operation to be executed.
F7
CAS
Column Address
Strobe
Referred to RAS
F9 WE Write Enable Referred to RAS
F1, E8
F2
F3
A9, E7, J9
A1, E3, J1
A7, B3, C7, D3
A3, B7, C3, D7
E2
UDQM,
LDQM
CLK
CKE
VDD
VSS
VDDQ
VSSQ
NC
Input/output
mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
Clock Inputs
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
Clock Enable When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power
Power for input buffers and logic circuit inside
DRAM.
Ground
Ground for input buffers and logic circuit inside
DRAM.
Power for I/O Separated power from VDD, to improve DQ noise
buffer
immunity.
Ground for I/O Separated ground from VSS, to improve DQ noise
buffer
immunity.
No Connection No connection
Publication Release Date: Jul. 17, 2014
- 5 - Revision: A05

5 Page





W9825G6JB arduino
W9825G6JB
7.17 Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCKS (min) + tCK (min).
7.18 No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS , CAS and WE held high at the rising edge of
the clock. A No Operation Command will not terminate a previous operation that is still executing, such
as a burst read or write cycle.
7.19 Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS , CAS and WE signals become don't
cares.
7.20 Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
- 11 -
Publication Release Date: Jul. 17, 2014
Revision: A05

11 Page







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