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PDF VS6663CC Datasheet ( Hoja de datos )

Número de pieza VS6663CC
Descripción 1.3 megapixel camera module
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo

Total 30 Páginas
		
VS6663CC Hoja de datos, Descripción, Manual
VS6663CC
Features
1280 x 960 1.3 Mpixel resolution sensor
Compact size: 6.5 mm x 6.5 mm x 4.1 mm
Short focus distance: 5cm
MIPI CSI-2(a) (D-PHY v1.0) and CCP2 Video
data interface
Ultra low power standby mode (<15uW)
Binning 2x2 mode
Defect correction
4-channel lens shading correction
1.3 megapixel camera module
Datasheet - production data
Description
The VS6663CC is a compact camera module
designed for imaging and machine vision
applications which require a short focus distance.
It is designed to be used for high quality still
camera function and also supports video modes.
The camera silicon device is capable of
generating raw Bayer 1.3 Mpixel images up to
30 fps. The VS6663CC supports the CCI control
and CCP2 and CSI-2 data interfaces.
The module design is optimized for both footprint
and height.
A separate hardware accelerator can be
incorporated in the phone system to run the
algorithms in hardware. The specification of these
devices are contained in a separate document.
Table 1. Device summary
Order code
Package
Packing
VS6663CCQ05I/1 SMIA65 Tape and reel
a. Copyright2005 MIPI Alliance, Inc. Standard for
Camera Serial Interface 2 (CSI-2) version 1.01, limited
to 1 Gbps per lane
October 2015
This is information on a product in full production.
Doc ID028526 Rev 1
1/63
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VS6663CC pdf
VS6663CC
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reference documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
System input clock frequency range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-up sequence timing constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-down sequence timing constraints for CSI2 communications . . . . . . . . . . . . . . . . . 17
POR cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Valid register data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General status registers [0x0000 to 0x001F] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Frame format description registers [0x0040 to 0x007F] . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Analog gain description [0x0080 to 0x0093] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data format description registers [0x00C0 to 0x00C7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Setup registers [0x0100 to 0x01FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Integration time and gain registers [0x0200 to 0x02FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Video timing registers [0x0300 to 0x03FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Image compression registers [0x0500 to 0x0501] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Test pattern registers [0x0600 to 0x0611] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Binning registers [0x0900 to 0x0902] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Integration time and gain parameter limit registers [0x1000 to 0x10FF]. . . . . . . . . . . . . . . 30
Video timing parameter limit registers [0x1100 to 0x11FF]. . . . . . . . . . . . . . . . . . . . . . . . . 31
Binning capability registers [0x1700 to 0x1713] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Binning register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
External clock frequency examples - 1.3 Mpixel resolution Raw10 30 fps . . . . . . . . . . . . . 42
Analog gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power supplies VDIG, VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
System clock - EXTCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Power down control - XSHUTDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
CCI interface - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
CCI interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CCP2 interface - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
CCP2 interface - timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
CSI-2 interface - high speed mode - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CSI-2 interface - low power mode - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CSI-2 interface - high speed mode - AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
CSI-2 interface - low power mode - AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Lens design characteristics for first source lens supplier . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Doc ID028526 Rev 1
5/63
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5 Page

VS6663CC arduino
VS6663CC
Device pinout
Pad number
Table 4. Pin description (continued)
Pad name
I/O type
Description
2
VANA
PWR
Analog power
10 VDIG
PWR
Digital power
System
3
4
XSHUTDOWN
EXTCLK
I
I
Power down control(2)
System clock input
Control
5 SCL I
Serial communication clock
6 SDA I/O Serial communication data
Data
8
CLK-
SubLVDS output Output qualifying clock
9
CLK+
SubLVDS output Output qualifying clock
11
DATA-
SubLVDS output Serial output data
12
DATA+
SubLVDS output Serial output data
ST test
TP
ST test pins
Do not connect(3)
1. No connection should be made to VCAP.
2. Signal is active low.
3. Test pins are not floating.
Doc ID028526 Rev 1
11/63
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