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PDF VND7140AJ-E Data sheet ( Hoja de datos )

Número de pieza VND7140AJ-E
Descripción Double channel high-side driver
Fabricantes STMicroelectronics　
Logotipo STMicroelectronics Logotipo



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No Preview Available ! VND7140AJ-E Hoja de datos, Descripción, Manual

VND7140AJ-E
Double channel high-side driver with MultiSense analog feedback
for automotive applications
Datasheet - production data
Features
Max transient supply voltage
VCC
Operating voltage range
VCC
Typ. on-state resistance (per Ch) RON
Current limitation (typ)
ILIMH
Standby current (max)
ISTBY
40 V
4 to 28 V
140 mΩ
12 A
0.5 µA
• Automotive qualified
• General
– Double channel smart high-side driver with
MultiSense analog feedback
– Very low standby current
– Compatible with 3 V and 5 V CMOS
outputs
• MultiSense diagnostic functions
– Multiplexed analog feedback of: load
current with high precision proportional
current mirror, VCC supply voltage and
TCHIP device temperature
– Overload and short to ground (power
limitation) indication
– Thermal shutdown indication
– OFF-state open-load detection
– Output short to VCC detection
– Sense enable/ disable
• Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Configurable latch-off on overtemperature
or power limitation with dedicated fault
reset pin
– Loss of ground and loss of VCC
– Reverse battery with external components
– Electrostatic discharge protection
Applications
• All types of Automotive resistive, inductive and
capacitive loads
• Specially intended for automotive signal lamps
(up to R10W or LED Rear Combinations)
Description
The VND7140AJ-E is a double channel high-side
driver manufactured using ST proprietary
VIPower® technology and housed in
PowerSSO-16 package. The device is designed
to drive 12 V automotive grounded loads through
a 3 V and 5 V CMOS-compatible interface,
providing protection and diagnostics.
The device integrates advanced protective
functions such as load current limitation, overload
active management by power limitation and
overtemperature shutdown with configurable
latch-off.
A FaultRST pin unlatches the output in case of
fault or disables the latch-off functionality.
A dedicated multifunction multiplexed analog
output pin delivers sophisticated diagnostic
functions including high precision proportional
load current sense, supply voltage feedback and
chip temperature sense, in addition to the
detection of overload and short circuit to ground,
short to VCC and OFF-state open-load. A sense
enable pin allows OFF-state diagnosis to be
disabled during the module low-power mode as
well as external sense resistor sharing among
similar devices.
October 2014
This is information on a product in full production.
DocID022375 Rev 9
1/48
www.st.com

1 page




VND7140AJ-E pdf
VND7140AJ-E
List of figures
List of figures
Figure 1.
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Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
IOUT/ISENSE versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Current sense accuracy versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Switching times and Pulse skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MultiSense timings (current sense mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MultiSense timings (chip temperature and VCC sense mode) . . . . . . . . . . . . . . . . . . . . . . 20
TDSTKON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) . . . . . . . . . . . 22
Latch functionality - behavior in hard short circuit condition . . . . . . . . . . . . . . . . . . . . . . . . 22
Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) 23
Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Standby state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
OFF-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
IGND(ON) vs. Iout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Logic Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Logic Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
High level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Logic Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FaultRST Input clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
On-state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
On-state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Won vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Woff vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
OFF-state open-load voltage detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Vsense clamp vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Vsenseh vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MultiSense and diagnostic – block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
MultiSense block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Analogue HSD – open-load detection in off-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Open-load / short to VCC condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
GND voltage shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) . . . . . . . . . . . . . . . . . . . . 39
PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) . . . . . . . . . . . . . . . . . . . . 39
PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . 40
PowerSSO-16 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 40
Thermal fitting model for PowerSSO-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
PowerSSO-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DocID022375 Rev 9
5/48
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VND7140AJ-E arduino
VND7140AJ-E
Electrical specification
Symbol
Table 5. Power section (continued)
Parameter
Test conditions
IL(off)
VF
Off-state output
current at
VCC = 13 V(1)
Output - VCC diode
voltage (1)
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 25 °C
VIN = VOUT = 0 V; VCC = 13 V;
Tj = 125 °C
IOUT = -1 A; Tj = 150 °C
1. For each channel
2. PowerMOS leakage included.
3. Parameter specified by design; not subject to production test.
Min. Typ. Max. Unit
0 0.01 0.5
µA
03
0.7 V
Table 6. Switching (VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified)
Symbol
Parameter
Test conditions Min. Typ. Max. Unit
td(on)(1)
td(off)(1)
Turn-on delay time at Tj = 25 °C RL = 13 Ω
Turn-off delay time at Tj = 25 °C
(dVOUT/dt)on(1)
Turn-on voltage slope at
Tj = 25 °C
(dVOUT/dt)off(1)
Turn-off voltage slope at
Tj = 25 °C
RL = 13 Ω
WON
Switching energy losses at
turn-on (twon)
RL = 13 Ω
WOFF
Switching energy losses at
turn-off (twoff)
RL = 13 Ω
tSKEW(1)
Differential Pulse skew
(tPHL - tPLH)
RL = 13 Ω
10 70 120
µs
10 40 100
0.1 0.27 0.7
V/µs
0.1 0.35 0.7
— 0.15 0.18(2) mJ
— 0.1 0.18(2) mJ
-100 -50 0 µs
1. See Figure 6: Switching times and Pulse skew.
2. Parameter guaranteed by design and characterization; not subject to production test.
Symbol
Table 7. Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C)
Parameter
Test conditions Min. Typ. Max. Unit
INPUT0,1 characteristics
VIL
IIL
VIH
IIH
VI(hyst)
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
VICL
Input clamp voltage
VIN = 0.9 V
VIN = 2.1 V
IIN = 1 mA
IIN = -1 mA
0.9
1
2.1
10
0.2
5.3 7.2
-0.7
V
µA
V
µA
V
V
DocID022375 Rev 9
11/48
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