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PDF GS2961 Data sheet ( Hoja de datos )
| Número de pieza | GS2961 | |
| Descripción | Receiver | |
| Fabricantes | Gennum | |
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GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer
complete with SMPTE Video Processing
Key Features
• Operation at 2.97Gb/s, 2.97/1.001Gb/s, 1.485Gb/s,
1.485/1.001Gb/s and 270Mb/s
• Supports SMPTE 425M (Level A and Level B), SMPTE
424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI
• Integrated adaptive cable equalizer
• Typical equalized length of Belden 1694A cable:
150m at 2.97Gb/s
250m at 1.485Gb/s
480m at 270Mb/s
• Integrated Reclocker with low phase noise, integrated
VCO
• Serial digital reclocked, or non-reclocked output
• Ancillary data extraction
• Optional conversion from SMPTE 425M Level B to
Level A for 1080p 50/60 4:2:2 10-bit
• Parallel data bus selectable as either 20-bit or 10-bit
• Comprehensive error detection and correction
features
• Output H, V, F or CEA 861 Timing Signals
• 1.2V digital core power supply, 1.2V and 3.3V analog
power supplies, and selectable 1.8V or 3.3V I/O power
supply
• GSPI Host Interface
• -20ºC to +85ºC operating temperature range
• Low power operation (typically 515mW)
• Small 11mm x 11mm 100-ball BGA package
• Pb-free and ROHS compliant
Errata
Refer to Errata document entitled GS2960/GS2961 Errata
for this device (document number 53117).
Applications
Application: Single Link (3G-SDI)
to Dual Link (HD-SDI) Converter
3G-SDI
GS2961
10-bit
HV F/PCLK
HV F/PCLK
10-bit
GS2962
GS2962
HD-SDI
Link A
HD-SDI
Link B
HD-SDI
Link A
HD-SDI
Link B
Application: Dual Link (HD-SDI)
to Single Link (3G-SDI) Converter
HD-SDI
Deserializer
GS2961
10-bit
HV F/PCLK
FIFO
WR
HD-SDI
Deserializer
GS2961
10-bit
HV F/PCLK
FIFO
WR
10-bit
HV F/PCLK
10-bit
GS2962
3G-SDI
GS4910
HVF
X TAL
Description
The GS2961 is a multi-rate SDI integrated Receiver which
includes complete SMPTE processing, as per SMPTE 425M,
292M and SMPTE 259M-C. The SMPTE processing features
can be bypassed to support signals with other coding
schemes.
The GS2961 integrates Gennum's adaptive cable equalizer
technology, achieving unprecedented cable lengths and
jitter tolerance. It features DC restoration to compensate for
the DC content of SMPTE pathological signals.
The device features an Integrated Reclocker with an
internal VCO and a wide Input Jitter Tolerance (IJT) of
0.7UI.
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
www.gennum.com
1 of 104
1 page  
4.11 Programmable Multi-function Outputs ............................................................................... 46
4.12 H:V:F Timing Signal Generation ............................................................................................ 47
4.12.1 CEA-861 Timing Generation ....................................................................................... 49
4.13 Automatic Video Standards Detection ................................................................................ 56
4.14 Data Format Detection & Indication ..................................................................................... 59
4.15 EDH Detection .............................................................................................................................. 60
4.15.1 EDH Packet Detection ................................................................................................... 60
4.15.2 EDH Flag Detection ........................................................................................................ 61
4.16 Video Signal Error Detection & Indication ......................................................................... 61
4.16.1 TRS Error Detection........................................................................................................ 63
4.16.2 Line Based CRC Error Detection ................................................................................ 63
4.16.3 EDH CRC Error Detection............................................................................................. 64
4.16.4 HD & 3G Line Number Error Detection ................................................................... 64
4.17 Ancillary Data Detection & Indication ................................................................................. 64
4.17.1 Programmable Ancillary Data Detection................................................................ 66
4.17.2 SMPTE 352M Payload Identifier ................................................................................ 67
4.17.3 Ancillary Data Checksum Error ................................................................................. 68
4.17.4 Video Standard Error..................................................................................................... 69
4.18 Signal Processing ......................................................................................................................... 69
4.18.1 TRS Correction & Insertion........................................................................................... 70
4.18.2 Line Based CRC Correction & Insertion ................................................................... 71
4.18.3 Line Number Error Correction & Insertion ............................................................. 71
4.18.4 ANC Data Checksum Error Correction & Insertion ............................................. 71
4.18.5 EDH CRC Correction & Insertion ............................................................................... 71
4.18.6 Illegal Word Re-mapping ............................................................................................. 72
4.18.7 TRS and Ancillary Data Preamble Remapping...................................................... 72
4.18.8 Ancillary Data Extraction............................................................................................. 72
4.18.9 Level B to Level A Conversion .................................................................................... 77
4.19 GSPI - HOST Interface ................................................................................................................ 77
4.19.1 Command Word Description ...................................................................................... 78
4.19.2 Data Read or Write Access........................................................................................... 79
4.19.3 GSPI Timing....................................................................................................................... 80
4.20 Host Interface Register Maps .................................................................................................. 82
4.21 JTAG Test Operation .................................................................................................................. 95
4.22 Device Power-up ......................................................................................................................... 97
4.23 Device Reset .................................................................................................................................. 97
4.24 Standby Mode .............................................................................................................................. 97
5. Application Reference Design ............................................................................................................... 98
5.1 High Gain Adaptive Cable Equalizers .................................................................................... 98
5.2 PCB Layout ....................................................................................................................................... 98
5.3 Typical Application Circuit ........................................................................................................ 99
6. References & Relevant Standards ....................................................................................................... 100
7. Package & Ordering Information ........................................................................................................ 101
7.1 Package Dimensions ................................................................................................................... 101
7.2 Packaging Data ............................................................................................................................. 102
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
5 of 104
5 Page 
Table 1-1: Pin Descriptions (Continued)
Pin
Number
C7
D4, E4, F4
D5, E5, F5,
G4, G5, H3
D6, E6, F6,
G6
D7
D8
E1
E2
E7
E8
Name
Timing
Type
Description
RESET_TRST
PLL_GND
CORE_GND
CORE_VDD
SW_EN
JTAG/HOST
EQ_VDD
EQ_GND
SDOUT_TDO
SDIN_TDI
Input
Input Power
Input Power
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings
and to reset the JTAG sequence.
Normal mode (JTAG/HOST = LOW):
When LOW, all functional blocks are set to default conditions and
all digital output signals become high impedance.
When HIGH, normal operation of the device resumes.
JTAG test mode (JTAG/HOST = HIGH):
When LOW, all functional blocks are set to default and the JTAG test
sequence is reset.
When HIGH, normal operation of the JTAG test sequence resumes
after RESET_TRST is de-asserted.
GND pins for the Reclocker PLL. Connect to analog GND.
GND connection for device core. Connect to digital GND.
Input Power POWER connection for device core. Connect to 1.2V DC digital.
Input
Input
Input Power
Input Power
Output
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable switch-line locking, as described in Section 4.10.1.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG test mode or host interface mode.
When JTAG/HOST is HIGH, the host interface port is configured for
JTAG test.
When JTAG/HOST is LOW, normal operation of the host interface
port resumes.
POWER pin for SDI buffer. Connect to 3.3V DC analog.
GND pin for SDI buffer. Connect to analog GND.
COMMUNICATION SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
GSPI serial data output/test data out.
In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test
results from the device.
In host interface mode, this pin is used to read status and
configuration data from the device.
COMMUNICATION SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
GSPI serial data in/test data in.
In JTAG mode (JTAG/HOST = HIGH), this pin is used to shift test data
into the device.
In host interface mode, this pin is used to write address and
configuration data words into the device.
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
11 of 104
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GS2961.PDF ] | |
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