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PDF R5F213G6ANNP Data sheet ( Hoja de datos )

Número de pieza R5F213G6ANNP
Descripción MCU
Fabricantes Renesas 
Logotipo Renesas Logotipo



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R8C/3GA Group
RENESAS MCU
REJ03B0235-0110
Rev.1.10
Sep. 10, 2009
1. Overview
1.1 Features
The R8C/3GA Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions
for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high
speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
The R8C/3GA Group has data flash (1 KB × 4 blocks) with the background operation (BGO) function.
1.1.1 Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
REJ03B0235-0110 Rev.1.10 Sep. 10, 2009
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R5F213G6ANNP pdf
R8C/3GA Group
1.3 Block Diagram
Figure 1.2 shows a Block Diagram.
1. Overview
I/O ports
Peripheral functions
Timers
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RE (8 bits × 1)
Watchdog timer
(14 bits)
A/D converter
(10 bits × 8 channels)
D/A converter
(8 bits × 2)
Figure 1.2 Block Diagram
4 8 4 31
Port P0
Port P1
Port P3
Port P4
UART or
clock synchronous serial I/O
(8 bits × 2)
I2C bus or SSU
(8 bits × 1)
LIN module
Comparator B
System clock generation
circuit
XIN-XOUT
Low-speed on-chip oscillator
XCIN-XCOUT
Low-speed on-chip oscillator
for watchdog timer
Voltage detection circuit
Comparator A
DTC
R8C CPU core
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
Memory
ROM (1)
RAM (2)
Multiplier
Notes:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
REJ03B0235-0110 Rev.1.10 Sep. 10, 2009
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R5F213G6ANNP arduino
R8C/3GA Group
2. Central Processing Unit (CPU)
2.1 Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-
bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5 Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2 Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5 Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
REJ03B0235-0110 Rev.1.10 Sep. 10, 2009
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