DataSheet.es    


PDF uPD46364185B Data sheet ( Hoja de datos )

Número de pieza uPD46364185B
Descripción 36M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION
Fabricantes Renesas 
Logotipo Renesas Logotipo



Hay una vista previa y un enlace de descarga de uPD46364185B (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! uPD46364185B Hoja de datos, Descripción, Manual

μPD46364185B
μPD46364365B
Datasheet
36M-BIT DDR II SRAM SEPARATE I/O
2-WORD BURST OPERATION
R10DS0092EJ0400
Rev.4.00
Nov 09, 2012
Description
The μPD46364185B is a 2,097,152-word by 18-bit and the μPD46364365B is a 1,048,576-word by 36-bit synchronous
double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The μPD46364185B and μPD46364365B integrate unique synchronous peripheral circuitry and a burst counter. All input
registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density and
wide bit configuration. These products are packaged in 165-pin PLASTIC BGA.
Features
1.8 ± 0.1 V power supply
165-pin PLASTIC BGA (13 x 15)
HSTL interface
PLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports
DDR read or write operation initiated each cycle
Pipelined double data rate operation
Separate data input/output bus
Two-tick burst for low DDR transaction size
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
Two output clocks (C and C#) for precise flight time and clock skew matching-clock
and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.
User programmable impedance output (35 to 70 Ω)
Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz)
Simple control logic for easy depth expansion
JTAG 1149.1 compatible test access port
R10DS0092EJ0400 Rev.4.00
Nov 09, 2012
Page 1 of 34

1 page




uPD46364185B pdf
μPD46364185B, μPD46364365B
Pin Description
Symbol
A
Type
Input
D0 to Dxx Input
Q0 to Qxx Output
LD#
R, W#
BWx#
Input
Input
Input
K, K#
Input
C, C#
Input
(1/2)
Description
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of K. All transactions operate on a burst of two words (one
clock period of bus activity). These inputs are ignored when device is deselected, i.e., NOP
(LD# = HIGH).
Synchronous Data Inputs: Input data must meet setup and hold times around the rising
edges of K and K# during WRITE operations. See Pin Arrangement for ball site location of
individual signals.
x18 device uses D0 to D17.
x36 device uses D0 to D35.
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K
and K# rising edges if C and C# are tied HIGH. Data is output in synchronization with C and
C# (or K and K#), depending on the LD# and R, W# command. See Pin Arrangement for
ball site location of individual signals.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined.
This definition includes address and read/write direction. All transactions operate on a burst
of 2 data (one clock period of bus activity).
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type
(READ when R, W# is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W#
must meet the setup and hold times around the rising edge of K.
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold times
around the rising edges of K and K# for each of the two rising edges comprising the WRITE
cycle. See Pin Arrangement for signal to data relationships.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See Byte Write Operation for relation between BWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising edge of
K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180
degrees out of phase with K. All synchronous inputs must meet setup and hold times around
the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output data.
The rising edge of C# is used as the output timing reference for first output data. The rising
edge of C is used as the output reference for second output data. Ideally, #C is 180 degrees
out of phase with C. When use of K and K# as the reference instead of C and C#, then fixed
C and C# to HIGH. Operation cannot be guaranteed unless C and C# are fixed to HIGH
(i.e. toggle of C and C#)
R10DS0092EJ0400 Rev.4.00
Nov 09, 2012
Page 5 of 34

5 Page





uPD46364185B arduino
μPD46364185B, μPD46364365B
Bus Cycle State Diagram
LOAD NEW
ADDRESS
Count = 0
Load, Count = 2
Read
Load, Count = 2
Write
READ DOUBLE
Count = Count + 2
WRITE DOUBLE
Count = Count + 2
NOP,
Count = 2
NOP
NOP
Power UP
Supply voltage provided
Remark State machine control timing sequence is controlled by K.
NOP,
Count = 2
Load
R10DS0092EJ0400 Rev.4.00
Nov 09, 2012
Page 11 of 34

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet uPD46364185B.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
uPD46364185B36M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATIONRenesas
Renesas

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar