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PDF uPD46364182B Data sheet ( Hoja de datos )

Número de pieza uPD46364182B
Descripción 36M-BIT DDR II SRAM 2-WORD BURST OPERATION
Fabricantes Renesas 
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μPD46364092B
μPD46364182B
μPD46364362B
Datasheet
36M-BIT DDR II SRAM
2-WORD BURST OPERATION
R10DS0091EJ0400
Rev.4.00
Nov 09, 2012
Description
The μPD46364092B is a 4,194,304-word by 9-bit, the μPD46364182B is a 2,097,152-word by 18-bit and the
μPD46364362B is a 1,048,576-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS
technology using full CMOS six-transistor memory cell.
The μPD46364092B, μPD46364182B and μPD46364362B integrate unique synchronous peripheral circuitry and a burst
counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA.
Features
1.8 ± 0.1 V power supply
165-pin PLASTIC BGA (13 x 15)
HSTL interface
PLL circuitry for wide output data valid window and future frequency scaling
Pipelined double data rate operation
Common data input/output bus
Two-tick burst for low DDR transaction size
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.
User programmable impedance output (35 to 70 Ω)
Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz)
Simple control logic for easy depth expansion
JTAG 1149.1 compatible test access port
R10DS0091EJ0400 Rev.4.00
Nov 09, 2012
Page 1 of 35

1 page




uPD46364182B pdf
μPD46364092B, μPD46364182B, μPD46364362B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
[μPD46364362B]
1M x 36
12345678
A CQ# VSS/144M A
R, W# BW2# K# BW1# LD#
B NC DQ27 DQ18 A BW3# K BW0# A
C NC
NC DQ28 VSS
A
A0
A
VSS
D NC DQ29 DQ19 VSS VSS VSS VSS VSS
E NC NC DQ20 VDDQ VSS VSS VSS VDDQ
F NC DQ30 DQ21 VDDQ VDD
VSS
VDD
VDDQ
G NC
DQ31 DQ22 VDDQ
VDD
VSS
VDD
VDDQ
H DLL# VREF VDDQ VDDQ
VDD
VSS
VDD
VDDQ
J NC
NC DQ32 VDDQ VDD
VSS
VDD
VDDQ
K NC
NC DQ23 VDDQ VDD
VSS
VDD
VDDQ
L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ
M NC NC DQ34 VSS VSS VSS VSS VSS
N NC DQ35 DQ25 VSS
A
A
A VSS
P NC
NC DQ26
A
A
C
A
A
R TDO TCK
A
A
A C# A
A
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
VSS/72M
NC
DQ17
NC
DQ15
NC
NC
VREF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
A0, A
DQ0 to DQ35
LD#
R, W#
BW0# to BW3#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
VREF
VDD
VDDQ
VSS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
Remarks 1. ×××# indicates active LOW.
2. Refer to Package Dimensions for the index mark.
3. 2A and 10A are expansion addresses : 10A for 72Mb
: 10A and 2A for 144Mb
2A and 10A of this product can also be used as NC.
R10DS0091EJ0400 Rev.4.00
Nov 09, 2012
Page 5 of 35

5 Page





uPD46364182B arduino
μPD46364092B, μPD46364182B, μPD46364362B
Byte Write Operation
[μPD46364092B]
Operation
K K#
Write DQ0 to DQ8
LH
LH
Write nothing
LH
LH
Remarks 1. H : HIGH, L : LOW, : rising edge.
BW0#
0
0
1
1
2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[μPD46364182B]
Operation
Write DQ0 to DQ17
Write DQ0 to DQ8
Write DQ9 to DQ17
Write nothing
K
LH
LH
LH
LH
K#
LH
LH
LH
LH
BW0#
0
0
0
0
1
1
1
1
BW1#
0
0
1
1
0
0
1
1
Remarks 1. H : HIGH, L : LOW, : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[μPD46364362B]
Operation
K
K#
BW0#
BW1#
BW2#
BW3#
Write DQ0 to DQ35
LH
0
0
0
0
LH
0
0
0
0
Write DQ0 to DQ8
LH
0
1
1
1
LH
0
1
1
1
Write DQ9 to DQ17
LH
1
0
1
1
LH
1
0
1
1
Write DQ18 to DQ26
LH
1
1
0
1
LH
1
1
0
1
Write DQ27 to DQ35
LH
1
1
1
0
LH
1
1
1
0
Write nothing
LH
1
1
1
1
LH
1
1
1
1
Remarks 1. H : HIGH, L : LOW, : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
R10DS0091EJ0400 Rev.4.00
Nov 09, 2012
Page 11 of 35

11 Page







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