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PDF M37225ECSP Data sheet ( Hoja de datos )

Número de pieza M37225ECSP
Descripción SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fabricantes Renesas 
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M37225M6/M8/MA/MC–XXXSP, M37225ECSP
SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
REJ03B0136-0100Z
Rev.1.00
Nov 01, 2000
1. DESCRIPTION
The M37225M6/M8/MA/MC–XXXSP are single-chip microcomput-
ers designed with CMOS silicon gate technology. They have a OSD,
I2C-BUS interface, PWM output, and 12 V withstand, so it is useful
for a channel selection system for TV.
The features of the M37225ECSP are similar to those of the
M37225M6-XXXSP except that the chip has a built-in PROM which
can be written electrically. The differences amang M37225M6/M8/
MA/MC–XXXSP are the ROM, RAM size. Accordingly, the following
descriptions will be for the M37225M6-XXXSP.
2. FEATURES
qNumber of basic instructions .................................................... 71
qMemory size
ROM ......... 24K bytes (M37225M6-XXXSP)
32K bytes (M37225M8-XXXSP)
40K bytes (M37225MA–XXXSP)
48K bytes (M37225MC–XXXSP, M37225ECSP)
RAM ......... 1024 bytes (M37225M6/M8-XXXSP)
2048 bytes (M37225MA/MC–XXXSP, M37225ECSP)
(ROM correction memory included)
qMinimum instruction execution time
......................................... 0.5 µs (at 8 MHz oscillation frequency)
qPower source voltage ................................................. 5 V ± 10 %
qSubroutine nesting ............................................. 128 levels (Max.)
qInterrupts ....................................................... 16 types, 16 vectors
q8-bit timers .................................................................................. 4
qProgrammable I/O ports (Ports P0, P1, P2, P30–P32, P35) ..... 28
qInput ports (Ports P33, P34, P50, P51) ........................................ 4
qOutput ports (Ports P52–P55) ..................................................... 4
q12 V withstand ports ................................................................... 6
qLED drive ports ........................................................................... 4
qSerial I/O ............................................................ 8-bit 1 channel
qMulti-master I2C-BUS interface .............................. 1 (2 systems)
qA-D converter (8-bit resolution) .................................... 8 channels
qPWM output circuit ........................................ 14-bit 2, 8-bit 6
qPower dissipation
In operating ...................................................................... 165 mW
(at VCC = 5.5V, 8 MHz oscillation frequency, and OSD on)
qROM correction function ................................................ 3 vectors
qImmediate return mode from wait state
qOSD function
Display characters ............................................... 24 characters 2 lines
(It is possible to display 3 lines or more by software)
Kinds of characters ......... 381 kinds
Character display area 16 20 dots
Kinds of character sizes .............................. Block display: 3 kinds
SPRITE display: 1 kinds
Kinds of character colors. ................................. 8 colors (R, G, B)
Coloring unit ................... character, character background, raster
Display position
Horizontal: 64 levels Vertical :255 levels
Attribute ........ Border (all-bordered, shadow-bordered), BUTTON
SPRITE display function
Wallpaper function
Window function
Corresponding to bi-scan mode
3. APPLICATION
TV
Rev.1.00 Nov 01, 2000 page 1 of 124
REJ03B0136-0100Z

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M37225ECSP pdf
M37225M6/M8/MA/MC-XXXSP, M37225ECSP
6. PERFORMANCE OVERVIEW
Table 6.1 Performance Overview
Parameter
Number of basic instructions
Instruction execution time
Clock frequency
Memory size
Input/Output
ports
ROM M37225M6-XXXSP
M37225M8-XXXSP
M37225MA-XXXSP
M37225MC-XXXSP,
M37225ECSP
RAM M37225M6/M8-XXXSP
M37225MA/MC-XXXSP,
M37225ECSP
OSD ROM
OSD RAM
P00–P05
I/O
P06, P07
I/O
P1 I/O
P2 I/O
P30, P31, P35
I/O
P32
P33, P34
P50, P51
I/O
Input
Input
P52–P55
Serial I/O
Multi-master I2C-BUS interface
A-D converter
PWM output circuit
Timers
ROM correction function
Subroutine nesting
Interrupt
Output
Clock generating circuit
Functions
71
0.5 µs (the minimum instruction execution time, at 8 MHz oscillation fre-
quency)
8 MHz (maximum)
24K bytes
32K bytes
40K bytes
48K bytes
1024 bytes (ROM correction memory included)
2048 bytes (ROM correction memory included)
15K bytes
96 bytes
6-bit 1 (N-channel open-drain output structure, can be used as PWM
output pins)
2-bit 1 (N-channel open-drain output structure, can be used as INT input
pins, A-D input pin)
8-bit 1 (CMOS input/output structure, can be used as OSD output pin, INT
input pin, A-D input pins, DA output pin, multi-master I2C-BUS interface)
8-bit 1 (CMOS input/output structure, can be used as serial I/O pins,
timer external clock input pins)
3-bit 1 (CMOS output structure, or N-channel open-drain output struc-
ture, can be used as A-D input pins, DA output pin)
1-bit 1 (N-channel open-drain output structure, can be used as A-D input pin)
2-bit 1 (Can be used as OSD clock input/output pins)
2-bit 1 (N-channel open-drain output structure, can be used as horizonal
• vertical synchronous sibnal input pins)
4-bit 1 (CMOS output structure, can be used as OSD output pins)
8-bit 1
1 (2 systems)
8 channels (8-bit resolution)
14-bit 2, 8-bit 6
8-bit timer 4
3 vectors
128 levels (maximum)
<16 types>
INT external interrupt 3, Internal timer interrupt 6, Serial I/O interrupt
1, OSD interrupt 1, Multi-master I2C-BUS interface interrupt 1,
f(XIN)/4096 interrupt 1, SPRITE OSD interrupt 1, A-D conversion inter-
rupt 1, VSYNC interrupt 1, BRK instruction interrupt 1, reset 1
2 built-in circuits (externally connected to a ceramic resonator or a quartz-
crystal oscillator)
Rev.1.00 Nov 01, 2000 page 5 of 124
REJ03B0136-0100Z

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M37225ECSP arduino
M37225M6/M8/MA/MC-XXXSP, M37225ECSP
8. FUNCTIONAL DESCRIPTION
8.1 CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses the standard 740 Family instruction set.
Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for de-
tails on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
8.1.1 CPU Mode Register
The CPU mode register contains the stack page selection bit and
internal system clock selection bit. The CPU mode register is allo-
cated at address 00FB16.
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 1 1 1 0 0 CPU mode register (CM) [Address 00FB16]
B Name
0, 1 Processor mode bits
(CM0, CM1)
2 Stack page selection
bit (CM2) (See note)
3 to 5 Fix these bits to “1.”
Functions
After reset R W
b1 b0
0 0: Single-chip mode
0 1:
1 0: Not available
1 1:
0 RW
0: 0 page
1: 1 page
1 RW
1 RW
6, 7 Fix these bits to “0.”
0 RW
Note: This bit is set to “1” after the reset release.
Fig. 8.1.1 CPU Mode Register
Rev.1.00 Nov 01, 2000 page 11 of 124
REJ03B0136-0100Z

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