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Número de pieza R5F364AENFB
Descripción MCU
Fabricantes Renesas 
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Datasheet
M16C/64A Group
RENESAS MCU
R01DS0032EJ0200
Rev.2.00
Feb 07, 2011
1. Overview
1.1 Features
The M16C/64A Group microcomputer (MCU) incorporates the M16C/60 Series CPU core and flash
memory, employing sophisticated instructions for a high level of efficiency. This MCU has 1 MB of address
space (expandable to 4 MB), and it is capable of executing instructions at high speed. In addition, the
CPU core boasts a multiplier for high-speed operation processing.
This MCU consumes low power, and supports operating modes that allow additional power control. The
MCU also uses an anti-noise configuration to reduce emissions of electromagnetic noise and is designed
to withstand electromagnetic interference (EMI). By integrating many of the peripheral functions, including
the multifunction timer and serial interface, the number of system components has been reduced.
1.1.1 Applications
This MCU can be used in audio components, cameras, televisions, household appliances, office
equipment, communication devices, mobile devices, industrial equipment, and other applications.
R01DS0032EJ0200 Rev.2.00
Feb 07, 2011
Page 1 of 88

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R5F364AENFB pdf
M16C/64A Group
1. Overview
Part No. R 5 F 3 6 4 A 6 D FA
Package type
FA: Package PRQP0100JD-B (100P6F-A)
FB: Package PLQP0100KB-A (100P6Q-A)
Property code
N: Operating temperature: -20°C to 85°C
D: Operating temperature: -40°C to 85°C
Memory capacity
Program ROM 1/RAM
6: 128 KB/12 KB
E: 256 KB/20 KB
K: 384 KB/31KB
M: 512 KB/31 KB
M16C/64A Group (100 pins)
16-bit MCU
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1 Part No., with Memory Size and Package
M1 6 C
R 5 F 3 6 4 A6 DF A
   X X X X X X X
Type No. (See Figure 1.1 “Part No., with Memory Size and Package”)
Running No. 0 to 9, A to Z (except for I, O, Q)
Week code (from 01 to 54)
Last digit of year
Figure 1.2 Marking Diagram (Top View)
R01DS0032EJ0200 Rev.2.00
Feb 07, 2011
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R5F364AENFB arduino
M16C/64A Group
1. Overview
1.6 Pin Functions
Table 1.6 Pin Functions for the 100-Pin Package (1/3)
Signal Name Pin Name I/O Power Supply
Description
Power supply
input
VCC1,
VCC2, VSS
I
-
Apply 2.7 to 5.5 V to pins VCC1 and VCC2 (VCC1 VCC2)
and 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS I
VCC1
This is the power supply for the A/D and D/A converters.
Connect the AVCC pin to VCC1, and connect the AVSS pin
to VSS.
Reset input
RESET
I
VCC1 Driving this pin low resets the MCU.
CNVSS
CNVSS
I
External data bus
width select input
BYTE
I
D0 to D7 I/O
VCC1
VCC1
VCC2
Input pin to switch processor modes. After a reset, to start
operating in single-chip mode, connect the CNVSS pin to
VSS via a resistor. To start operating in microprocessor
mode, connect the pin to VCC1.
Input pin to select the data bus of the external area. The data
bus is 16 bits when it is low, and 8 bits when it is high. This
pin must be fixed either high or low. Connect the BYTE pin to
VSS in single-chip mode.
Inputs or outputs data (D0 to D7) while accessing an
external area with a separate bus.
D8 to D15 I/O
VCC2
Inputs or outputs data (D8 to D15) while accessing an
external area with a 16-bit separate bus.
A0 to A19
A0/D0 to
A7/D7
O
I/O
A1/D0 to
A8/D7
I/O
CS0 to CS3 O
Bus control pins
WRL/WR
WRH/BHE
RD
O
ALE
HOLD
HLDA
RDY
O
I
O
I
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
Outputs address bits A0 to A19.
Inputs or outputs data (D0 to D7) and outputs address bits
(A0 to A7) by timesharing, while accessing an external area
with an 8-bit multiplexed bus.
Inputs or outputs data (D0 to D7) and outputs address bits
(A1 to A8) by timesharing, while accessing an external area
with a 16-bit multiplexed bus.
Outputs chip-select signals CS0 to CS3 to specify an
external area.
Outputs WRL, WRH, (WR, BHE), and RD signals. WRL and
WRH can be switched with BHE and WR.
WRL, WRH, and RD selected
If the external data bus is 16 bits, data is written to an even
address in an external area when WRL is driven low. Data
is written to an odd address when WRH is driven low. Data
is read when RD is driven low.
WR, BHE, and RD selected
Data is written to an external area when WR is driven low.
Data in an external area is read when RD is driven low. An
odd address is accessed when BHE is driven low. Select
WR, BHE, and RD when using an 8-bit external data bus.
Outputs an ALE signal to latch the address.
HOLD input is unavailable. Connect the HOLD pin to VCC2
via a resistor (pull-up).
In a hold state, HLDA outputs a low-level signal.
The MCU bus is placed in a wait state while the RDY pin is
driven low.
Power supply: VCC2 is used to supply power to the external bus associated pins. The dual power supply configuration
allows VCC2 to interface at a different voltage than VCC1.
R01DS0032EJ0200 Rev.2.00
Feb 07, 2011
Page 11 of 88

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