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PDF M62352FP Data sheet ( Hoja de datos )
| Número de pieza | M62352FP | |
| Descripción | 8-bit 12ch D/A Converter | |
| Fabricantes | Renesas | |
| Logotipo |  |
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Preliminary Datasheet
M62352P/FP/GP
8-bit 12ch D/A Converter with Buffer Amplifiers
R03DS0041EJ0400
Rev.4.00
Jun 03, 2011
Description
The M62352 is an integrated circuit semiconductor of CMOS structure with 12 channels of built-in D/A converters with
output buffer operational amplifiers.
The 3-wire serial interface method is used for the transfer format of digital data to allow connection with
microcomputer with minimum wiring.
It is able to cascading serial use with DO terminal.
The output buffer operational amplifier operates in the whole voltage range from power supply to ground for both
input/output.
Features
12-bit serial data input (3-wire serial data transfer method)
Highly stable output buffer operational amplifier allow operation in the all voltage range from power supply to
ground.
Application
Adjustment/control of industrial or home-use electronic equipment, such as VTR camera, VTR set, TV, and CRT
display.
Block Diagram
GND
20
AO2
AO1
DI CLK LD
DO
AO12
AO11
VCC
19 18 17 16 15 14 13 12 11
8-bit R-2R
+ segment
D/A converter
Ch2
8-bit
latch
....
(12)
D/A
1
L
12-bit shift register
D0 1 2 3 4 5 6 D7 D8 9 10 D11
(8)
(12)
Address
decoder
........
D/A
12
L
D/A
11
L
(12)
8-bit
latch
Ch3
8-bit R-2R
+ segment
D/A converter
L
4
D/A
L
5
D/A
L
6
D/A
L
7
D/A
L
8
D/A
L
9
D/A
L
10
D/A
Buffer
OP AMP
1 2 3 4 5 6 7 8 9 10
VSS
(VrefL)
AO3
AO4
AO5
AO6
AO7
AO8
AO9
AO10 VDD
(VrefU)
R03DS0041EJ0400 Rev.4.00
Jun 03, 2011
Page 1 of 9
1 page  
M62352P/FP/GP
Preliminary
AC Characteristics
(VCC, VrefU = +5 V 10%, VCC VrefU, GND, VrefL = 0 V, Ta = –20 to +85C, unless otherwise noted)
Limits
Item
Symbol Min Typ Max Unit
Test Conditions
Clock "L" pulse width
tCKL
200 —
— ns
Clock "H" pulse width
tCKH
200 —
— ns
Clock rise time
tCR — — 200 ns
Clock fall time
tCF — — 200 ns
Data setup time
tDCH 30 — — ns
Data hold time
tCHD 60 — — ns
LD setup time
tCHL
200 —
— ns
LD hold time
tLDC
100 —
— ns
LD "H" pulse width
tLDH
100 —
— ns
Data output delay time
tDO
70 — 350 ns CL 100 pF
D/A output setting time
tLDD
— — 300 s CL 100 pF VAO: 0.5 4.5 V
The time until the output becomes
the final value of 1/2 LSB
Timing Chart
tCR
tCKH
tCF
CLK
DI
LD
tCKL
tDCH
tCHD
tCHL
tLDH
tLDC
D/A
output
DO
output
tLDD
tDO
R03DS0041EJ0400 Rev.4.00
Jun 03, 2011
Page 5 of 9
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet M62352FP.PDF ] | |
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