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PDF M62334P Data sheet ( Hoja de datos )

Número de pieza M62334P
Descripción 8-bit 4ch I2C BUS D/A Converter
Fabricantes Renesas 
Logotipo Renesas Logotipo



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Preliminary Datasheet
M62334P/FP, M62339P/FP
R03DS0039EJ0500
8-bit 4ch I2C BUS D/A Converter with Buffer Amplifiers
Rev.5.00
Jun 03, 2011
Description
The M62334/M62339 is an integrated circuit semiconductor of CMOS structure with 4 channels of built in D/A
converters with output buffer operational amplifiers.
The input is 2-wires serial method is used for the transfer format of digital data to allow connection with a
microcomputer with minimum wiring.
The output buffer operational amplifier employs AB class output circuit with sync and source drive capacity of 1.0 mA
or more, and it operates in the whole voltage range from VCC to ground.
The M62334 and the M62339 differ only in their slave address.
Features
Digital data transfer format: I2C BUS serial data method
Output buffer operational amplifier
It operates in the whole range from VCC to ground.
High output current drive capacity: 1.0 mA over
Application
Conversion from digital data to analog control data for home-use and industrial equipment.
Signal gain control or automatic adjustment of display-monitor or CTV.
Block Diagram
VCC SCL SDA
8 76
GND
5
Power on
reset
I2C BUS transceiver
Channel
decoder
8
8-bit latch
8-bit latch
8-bit latch
8-bit latch
8-bit upper
8-bit upper
8-bit upper
8-bit upper
segment R-2R segment R-2R segment R-2R segment R-2R
+−
+−
+−
+−
123 4
AO1
AO2
AO3
AO4
R03DS0039EJ0500 Rev.5.00
Jun 03, 2011
Page 1 of 9

1 page




M62334P pdf
M62334P/FP, M62339P/FP
Preliminary
I2C BUS Format
STA
Slave address
WA
Sub address
A DAC data
Note: STA: start condition, A: affirmation bit, W: write (SDA = Low), STP: stop condition
A STP
Slave address
M62334
First
Last
1001100
M62339
First
Last
1001111
Sub address
First
XXXXX
Don't care
Last
X S1 S0
Channel
select data
Channel select data
S1 S0
Channel Selection
0 0 ch1 selection
0 1 ch2 selection
1 0 ch3 selection
1 1 ch4 selection
DAC data
First
MSB
Last
LSB
D7 D6 D5 D4 D3 D2 D1 D0
First
MSB
Last
LSB
D7 D6 D5 D4 D3 D2 D1 D0
DAC output
0 0 0 0 0 0 0 0 VCC / 256 × 1
0 0 0 0 0 0 0 1 VCC / 256 × 2
0 0 0 0 0 0 1 0 VCC / 256 × 3
0 0 0 0 0 0 1 1 VCC / 256 × 4
::::::::
:
1 1 1 1 1 1 1 0 VCC / 256 × 255
1 1 1 1 1 1 1 1 VCC
R03DS0039EJ0500 Rev.5.00
Jun 03, 2011
Page 5 of 9

5 Page










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