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PDF M5M5T5672TG-20 Data sheet ( Hoja de datos )
| Número de pieza | M5M5T5672TG-20 | |
| Descripción | 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Preliminary
Notice: This is not final specification.
Some parametric limits are subject to change.
DESCRIPTION
The M5M5T5672TG is a family of 18M bit synchronous SRAMs
organized as 262144-words by 72-bit. It is designed to eliminate
dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Renesas's SRAMs are
fabricated with high performance, low power CMOS technology,
providing greater reliability. M5M5T5672TG operates on a single
2.5V power supply and are 2.5V CMOS compatible.
FEATURES
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 200 MHz
• Fast access time: 3.2 ns
• Single 2.5V –5% and +5% power supply VDD
• Individual byte write (BWa# - BWh#) controls may be tied
LOW
• Single Read/Write control pin (W#)
• Snooze mode (ZZ) for power down
• Linear or Interleaved Burst Modes
• JTAG boundary scan support
APPLICATION
High-end networking products that require high bandwidth, such
as switches and routers.
Renesas LSIs
M5M5T5672TG – 20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
FUNCTION
Synchronous circuitry allows for precise cycle control triggered
by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs,
all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),
Byte Write Enables (BWa#, BWb#, BWc#, BWd#, BWe#, BWf#,
BWg#, BWh#) and Read/Write (W#).
Write operations are controlled by the eight Byte Write
Enables (BWa# - BWh#) and Read/Write(W#) inputs. All writes
are conducted with on-chip synchronous self-timed write
circuitry.
Asynchronous inputs include Output Enable (G#), Clock (CLK)
and Snooze Enable (ZZ).
The HIGH input of ZZ pin puts the SRAM in the power-down
state.
The Linear Burst order (LBO#) is DC operated pin. LBO# pin
will allow the choice of either an interleaved burst, or a linear
burst.
All read, write and deselect cycles are initiated by the ADV
Low input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
PACKAGE
M5M5T5672TG
Bump
209(11X19) bump BGA
Body Size
14mm X 22mm
Bump Pitch
1mm
PART NAME TABLE
Part Name
M5M5T5672TG -20
Access
3.2ns
Cycle
5.0ns
Active Current
(max.)
450mA
Standby Current
(max.)
30mA
1/24
Preliminary
M5M5T5672TG-20 REV.1.0
1 page  
Renesas LSIs
M5M5T5672TG – 20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
DC OPERATED TRUTH TABLE
Name
Input Status
Operation
LBO#
HIGH or NC
LOW
Interleaved Burst Sequence
Linear Burst Sequence
Note4. LBO# is DC operated pin.
Note5. NC means No Connection.
Note6. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence.
BURST SEQUENCE TABLE
(1) Interleaved Burst Sequence (when LBO# = HIGH or NC)
Operation
A17~A2
First access, latch external address
A17~A2
Second access(first burst address)
latched A17~A2
Third access(second burst address)
latched A17~A2
Fourth access(third burst address)
latched A17~A2
0,0
0,1
1,0
1,1
A1,A0
0,1 1,0
0,0 1,1
1,1 0,0
1,0 0,1
1,1
1,0
0,1
0,0
(2) Linear Burst Sequence (when LBO# = LOW)
Operation
A17~A2
First access, latch external address
A17~A2
Second access(first burst address)
latched A17~A2
Third access(second burst address)
latched A17~A2
Fourth access(third burst address)
latched A17~A2
Note7. The burst sequence wraps around to its initial state upon completion.
0,0
0,1
1,0
1,1
A1,A0
0,1 1,0
1,0 1,1
1,1 0,0
0,0 0,1
1,1
0,0
0,1
1,0
TRUTH TABLE
E1# E2 E3# ADV W# BWx# G# CKE# ZZ# CLK Address used
Operation
H X X L X X X L L L->H
None
Deselect Cycle
X L X L X X X L L L->H
None
Deselect Cycle
X X H L X X X L L L->H
None
Deselect Cycle
X X X H X X X L L L->H
None
Continue Deselect Cycle
L H L L H X L L L L->H
External
Read Cycle, Begin Burst
X X X H X X L L L L->H
Next Read Cycle, Continue Burst
L H L L H X H L L L->H
External
NOP/Dummy Read, Begin Burst
X X X H X X H L L L->H
Next Dummy Read, Continue Burst
L H L L L L X L L L->H
External
Write Cycle, Begin Burst
X X X H X L X L L L->H
Next Write Cycle, Continue Burst
L H L L L H X L L L->H
None
NOP/Write Abort, Begin Burst
X X X H X H X L L L->H
Next Write Abort, Continue Burst
X X X X X X X H L L->H
Current
Ignore Clock edge, Stall
XXX X X X X X H
X
None
Snooze Mode
Note8. “H” = input VIH; “L” = input VIL; “X” = input VIH or VIL.
Note9. BWx#=H means all Synchronous Byte Write Enables (BWa#,BWb#,BWc#,BWd#) are HIGH. BWx#=L means one or more
Synchronous Byte Write Enables are LOW.
Note10. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5/24
Preliminary
M5M5T5672TG-20 REV.1.0
5 Page 
(3)READ TIMING
Renesas LSIs
M5M5T5672TG – 20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
CLK
tckeVKH
CKE#
tEVKH
E#
tadvVKH
ADV
tWVKH
W#
tKHKH
tKHKL
tKHckeX
tKLKH
tKHEX
tKHadvX
tKHWX
BWx#
tAVKH
tKHAX
ADD A1 A2
A3
DQ
G#
tKHQX1
Q(A1)
tKHQV tKHQX
Q(A2)
tGLQV
Q(A2+1)
Q(A2+2)
tGHQZ
Q(A2+3)
tGLQX1
Q(A2)
tKHQZ
Q(A3)
Q(A3+1)
Read A1 Read A2 Burst Read Stall Burst Read Burst Read Burst Read Deselect Continue Read A3 Burst Read Burst Read Burst Read
A2+1
A2+2
A2+3
A2
Deselect
A3+1
A3+2
A3+3
DON'T CARE
UNDEFINED
Note28.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An.
Note29. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW.
Note30.ZZ is fixed LOW.
11/24
Preliminary
M5M5T5672TG-20 REV.1.0
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet M5M5T5672TG-20.PDF ] | |
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