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PDF BD35395FJ-M Data sheet ( Hoja de datos )

Número de pieza BD35395FJ-M
Descripción Termination Regulator
Fabricantes ROHM Semiconductor 
Logotipo ROHM Semiconductor Logotipo



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Datasheet
Regulator IC Series for Automotive
Termination Regulator
for DDR-SDRAMs
BD35395FJ-M
General Description
BD35395FJ-M is a termination regulator compatible with
JEDEC DDR1/2/3/3L-SDRAM, which functions as a linear
power supply incorporating an N-channel MOSFET and
provides a sink/source current capability up to 1A
respectively. A built-in high-speed OP-AMP specially
designed offers an excellent transient response.
Requires 3.3 volts or 5.0 volts as a bias power supply to
drive the N-channel MOSFET. Has an independent
reference voltage input pin (VDDQ) and an independent
feedback pin (VTTS) to maintain the accuracy in voltage
required by JEDEC, and offers an excellent output voltage
accuracy and load regulation.
Features
Incorporates a push-pull power supply for
termination (VTT).
Incorporates an enabler.
Incorporates an under voltage lockout (UVLO).
Employs SOP-J8 package : 4.9×6.0×1.65(mm).
Incorporates a thermal shutdown protector (TSD).
Operates with input voltage from 2.7 to 5.5 volts.
Compatible with Dual Channel
(DDR1,DDR2,DDR3/DDR3L)
Incorporates PGOOD function.
Key Specifications
Input Voltage Range:
Termination Input Voltage:
VDDQ Reference Voltage:
Output Current:
Upper Side ON Resistance:
Lower Side ON Resistance:
Standby Current:
Operating Temperature Range:
2.7V to 5.5V
1.0V to 5.5V
1.0V to 2.75V
-1.01.0A(Max)
0.35(Typ)
0.35(Typ)
0.5mA (Typ)
-40°C to +105°C
Package(s)
SOP-J8
W(Typ) x D(Typ) x H(Max)
4.90mm x 6.00mm x 1.65mm
Applications
Power supply for DDR1/2/3/3L SDRAM
SOP-J8
Product structure : Silicon monolithic integrated circuit
.www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 14 • 001
This product has no designed protection against radioactive rays
1/16
TSZ02201-0R6R0AN00610-1-2
5.Jun.2014 Rev.002

1 page




BD35395FJ-M pdf
BD35395FJ-M
Datasheet
Electrical Characteristics(Unless otherwise specified Ta=25, VCC=3.3V, VEN=3V, VDDQ=1.8V, VTT_IN=1.8V)
Parameter
Symbol
MIN
Limit
TYP
MAX
Unit
Condition
Standby Current
IST -
0.5 1.0 mA VEN=0V
Bias Current
ICC - 2 4 mA VEN=3V
[Enable]
High Level Enable Input Voltage VENHIGH
2.3
-
5.5 V
Low Level Enable Input Voltage VENLOW
-0.3
-
0.8 V
Enable Pin Input Current
IEN -
7 10 µA VEN=3V
[Termination]
Termination Output Voltage
(DDR2)
Termination Output Voltage
(DDR1)
Termination Output Voltage
(DDR3)
Termination Output Voltage
(DDR3L)
Source current
VTT2
VTT1
1/2×VDDQ
-30m
1/2×VDDQ
1/2×VDDQ
+30m
1/2×VDDQ
-30m
1/2×VDDQ
1/2×VDDQ
+30m
VTT3
1/2×VDDQ
-15m
1/2×VDDQ
1/2×VDDQ
+15m
VTT3L
1/2×VDDQ
-13.5m
1/2×VDDQ
1/2×VDDQ
+13.5m
ITT+
1.0
-
-
V
ITT=-1.0A to 1.0A
Ta=-40to 105
VCC = 5.3V, VDDQ = 2.5V
V
VTT_IN = 2.5V
ITT=-1.0A to 1.0A
Ta=-40to 105
VCC = 3.3V, VDDQ =1.5V
V
VTT_IN =1.5V
ITT=-1.0A to 1.0A
Ta=-40to 105
VCC=3.3V, VDDQ=1.35V,
V
VTT_IN=1.35V
ITT=-1.0A to 1.0A
Ta=-40to 105
A
Sink current
ITT- -
- -1.0 A
Load Regulation
VTT
-
- 50 mV ITT=-1.0A to 1.0A
Upper Side ON Resistance
HRON
-
0.35 0.65 Ω
Lower Side ON Resistance
LRON
-
0.35 0.65 Ω
[VREF]
Input Impedance
ZVDDQ
140
200
260 kΩ
[PGOOD]
VTT PGOOD Low
Threshold voltage
VTT PGOOD High
Threshold Voltage
PGOOD output ON resistor
PGDLow
PGDHigh
PGDRon
-
1/2×VDDQ
-30m
-
-
1/2×VDDQ
+30m
-
- 10 20
V
V
Ω
PGOOD output leakage current PGDleak
-
-
1 µA PGOOD=6V
PGOOD delay time
PGDdelay
1
2
4 Ms
[UVLO]
Threshold Voltage
VUVLO
2.35
2.50
2.65 V VCC : sweep up
Hysteresis Voltage
VUVLO
120
180
240 mV VCC : sweep down
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
5/16
TSZ02201-0R6R0AN00610-1-2
5.Jun.2014 Rev.002

5 Page





BD35395FJ-M arduino
BD35395FJ-M
Datasheet
Power Dissipation
Thermal design must be conducted with the operation under the conditions listed below (which are the guaranteed
temperature range requiring consideration on appropriate margins etc);
1: Ambient temperature Ta: 105or lower
2:Chip junction temperature Tj: 150or lower
The chip junction temperature Tj can be considered as follows:
Most of heat loss in BD35395FJ-M occurs at the output N-channel FET. The power lost is determined by multiplying the
voltage between VIN and Vo by the output current. As this IC employs the power PKG, the thermal derating characteristics
significantly depends on the pc board conditions. When designing, care must be taken to the size of a pc board to be
used.
Power consumption (W) = Input voltage (VTT_IN)-Output voltage (VTT1/2VDDQ) ×Io(Ave)
Example) Where VTT_IN =1.8V, VDDQ=1.8V, Io(Ave)= 0.5A
Power consumption(W) = 1.8(V)-0.9(V) ×0.5(A)
= 0.45(W)
Heat dissipation characteristics
[W]
0.7
(1) 0.675W
0.6
0.5
(2) 0.563W
0.4
0.3
0.2
105
0.1
0
0
25 50 75 100 125 150
Ambient temperature [Ta]
[]
(1) mounted on 70mm×70mm×1.6mm glass-epoxy board
θj-c=185.2/W
(2) With no heat sink
θj-a=222.2/W
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
11/16
TSZ02201-0R6R0AN00610-1-2
5.Jun.2014 Rev.002

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