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PDF P4C1682 Data sheet ( Hoja de datos )

Número de pieza P4C1682
Descripción STATIC CMOS RAM
Fabricantes PYRAMID 
Logotipo PYRAMID Logotipo



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P4C1681, P4C1682
ULTRA HIGH SPEED 4K x 4
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 12/15/20/25 ns (Commercial)
– 20/25/35ns (Military)
Low Power Operation
Single 5V ± 10%Power Supply
Separate Inputs and Outputs
– P4C1681 Input Data at Outputs during Write
– P4C1682 Outputs in High Z during Write
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP
– 24-Pin 300 mil SOIC
– 24-Pin 300 mil SOJ
– 24-Pin Solder Seal Flat Pack
– 28-Pin LCC (450 mil x 450 mil)
DESCRIPTION
The P4C1681 and P4C1682 are 16,384-bit (4K x 4) ultra
high speed static RAMs similar to the P4C168, but with
separate data I/O pins. The P4C1681 features a
transparent write operation; the outputs of the P4C1682
are in high impedance during the write cycle. All devices
have low power standby modes. The RAMs operate
from a single 5V ± 10% tolerance power supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
.CMOS is used to reduce power consumption.
The P4C1681 and P4C1682 are available in 24-pin 300 mil
DIP, SOIC, Solder Seal Flatpack, and SOJ packages, as
well as a 28-pin LCC package, providing excellent board
level densities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P4,C4), SOIC (S4), SOJ (J4)
SOLDER SEAL FLAT PACK (FS-1)
LCC (L5-1)
Document # SRAM109 REV A
Revised October 2005
1

1 page




P4C1682 pdf
P4C1681, P4C1682
AC ELECTRICAL CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Symbol
Parameter
-12 -15
-20 -25 -35 Unit
Min Max Min Max Min Max Min Max Min Max
tWC Write Cycle Time 12
tCW Chip Enable Time 12
to End of Write
15 18
15 18
20 30 ns
20 25 ns
tAW Address Valid to 12
End of Write
15 18
20 25 ns
tAS Address Set-up
Time
0
00
0 0 ns
tWP Write Pulse Width 12
tAH Address Hold
Time
0
15 18
00
20 25 ns
0 0 ns
tDW Data Valid to
End of Write
7
8 10 10 15 ns
tDH Data Hold Time
tWZ Write Enable to
Output in High Z
0
4
00
5
0 0 ns
7 7 13 ns
tOW Output Active to
End of Write
0
00
0 0 ns
tAWE Write Enable to
Data-out Valid£
12 15 20 25 30 ns
tADV Data-in Valid to
Data-out Valid
12 15 20 25 30 ns
P4C1682 only.
£ P4C1681 only.
WRITE CYCLE NO. 1 (WE controlled)(10)
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. If CE goes HIGH simultaneously with WE HIGH, the output
remains in a high impedance state.
Document # SRAM109 REV A
12. Write Cycle Time is measured from the last valid address to the
first transitioning address.
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