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Número de pieza | P4C1299 | |
Descripción | STATIC CMOS RAM | |
Fabricantes | PYRAMID | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de P4C1299 (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
No Preview Available ! FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 15/20/25/35 ns (Commercial/Industrial)
– 15/20/25/35/45 ns (Military)
Low Power Operation
Single 5V±10% Power Supply
Output Enable (OE) & Chip Enable (CE1 and CE2)
Control Functions
P4C1299/P4C1299L
ULTRA HIGH SPEED 64K x 4
STATIC CMOS RAM
Data Retention with 2.0V Supply (P4C1299L)
Three-State Outputs
TTL/CMOS Compatible Outputs
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350x550 mil LCC
DESCRIPTION
The P4C1299 and P4C1299L are a 262,144-bit ultra high-
speed static RAM organized as 64K x 4.The CMOS memory
requires no clock or refreshing and has equal access and
cycle times. Inputs and outputs are fully TTL-compatible.
The RAM operates from a single 5V±10% tolerance power
supply. With battery backup (P4C1299LOnly), data integrity
is maintained for supply voltages down to 2.0V. Current
drain is typically 10 µA from a 2.0V supply.
Access times as fast as 15 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption.
The P4C1299 and P4C1299L are available in a 28-pin
300 mil DIP or SOJ, as well as a 28-pin 350x550 mil LCC
package, providing excellent board level densities.
Functional Block Diagram
Pin ConfigurationS
Document # SRAM144 REV OR
DIP (P5, C5)
SOJ (J5)
LCC (L5)
Created Nov 2012
1 page P4C1299/P4C1299L - ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym Parameter
-15
Min Max
tWC Write Cycle Time
10
tCW Chip Enable Time to End of Write
8
tAW Address Valid to End of Write
8
tAS Address Setup Time
0
tWP Write Pulse Width
8
tAH Address Hold Time
0
tDW Data Valid to End of Write
7
tDH Data Hold Time
0
tWZ Write Enable to Output in High Z
6
tOW Output Active from End of Write
0
-20
Min Max
12
10
10
0
10
0
8
0
7
0
-25
Min Max
15
12
12
0
12
0
10
0
8
0
-35
Min Max
20
15
15
0
15
0
12
0
10
0
-45
Min Max
25
18
18
0
18
0
15
0
15
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING WAVEFORM OF WRITE Cycle No. 1 (WE Controlled)(9)
Notes:
10. CE1,2 and WE must be LOW for WRITE cycle.
11. OE is LOW for this WRITE cycle to show tWZ and tOW.
12. If CE1,2 goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document #SRAM144 REV OR
Page 5
5 Page P4C1299/P4C1299L - ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM
REVISIONS
DOCUMENT NUMBER SRAM 144
DOCUMENT TITLE
P4C1299/P4C1299L - ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM
REV ISSUE DATE ORIGINATOR DESCRIPTION OF CHANGE
OR Nov-2012
JDB New Data Sheet
Document #SRAM144 REV OR
Page 11
11 Page |
Páginas | Total 11 Páginas | |
PDF Descargar | [ Datasheet P4C1299.PDF ] |
Número de pieza | Descripción | Fabricantes |
P4C1299 | STATIC CMOS RAM | PYRAMID |
P4C1299L | STATIC CMOS RAM | PYRAMID |
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