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PDF P4C1041L Data sheet ( Hoja de datos )
| Número de pieza | P4C1041L | |
| Descripción | STATIC CMOS RAM | |
| Fabricantes | PYRAMID | |
| Logotipo |  |
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FEATURES
Fast Access Time - 55 ns
Low Power Operation
Single 5V±10% Power Supply
2.0V Data Retention
Easy Memory Expansion Using CE and OE Inputs
Fully TTL Compatible Inputs and Outputs
P4C1041L
LOW POWER 256K x 16 (4 MEG)
STATIC CMOS RAM
Advanced CMOS Technology
Fast tOE
Automatic Power Down when deselected
Packages
– 44-Pin 400 mil TSOP II
DESCRIPTION
The P4C1041L is a 262,144 words by 16 bits high-speed
CMOS static RAM. The CMOS memory requires no clocks
or refreshing, and has equal access and cycle times. In-
puts are fully TTL-compatible. The RAM operates from a
single 5.0V ± 10% tolerance power supply.
Access times of 55 nanoseconds permit greatly enhanced
system operating speeds. CMOS is utilized to reduce
power consumption to a low level.
The P4C1041L device provides asynchronous operation
with matching access and cycle times. Memory locations
are specified on address pins A0 to A17. Reading is accom-
plished by device selection (CE) and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE or OE is HIGH or WE is LOW.
The P4C1041L comes in a 44-Pin 400 mil TSOP II pack-
age.
Functional Block Diagram
Pin Configuration
Document # SRAM142 REV OR
TSOP II
Revised March 2011
1 page  
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym Parameter
-55
Min Max
tWC Write Cycle Time
55
tAW Address Valid to End of Write
50
tCW Chip Enable to End of Write
50
tAS Address Setup Time
0
tWP Write Pulse Width
45
tWR Write Recovery Time
0
tDW Data to Write Time Overlap
25
tDH Data Hold from End of Write Time
0
tOW Output Active from End of Write
5
tWZ Write to Output in High-Z
20
tBW Byte Enable to End of Write
45
P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING WAVEFORM OF WRITE Cycle No. 1 (CE Controlled)
Document # SRAM142 REV OR
Page 5
5 Page 
REVISIONS
P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM
DOCUMENT NUMBER SRAM 142
DOCUMENT TITLE
P4C1041L - LOW POWER 256K X 16 STATIC CMOS RAM
REV ISSUE DATE ORIGINATOR DESCRIPTION OF CHANGE
OR Mar-2011
JDB New Data Sheet
Document # SRAM142 REV OR
Page 11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet P4C1041L.PDF ] | |
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