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PDF LTC3816 Data sheet ( Hoja de datos )
| Número de pieza | LTC3816 | |
| Descripción | DC/DC Controller | |
| Fabricantes | Linear | |
| Logotipo |  |
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LTC3816
Features
Single-Phase Wide VIN
Range DC/DC Controller for
Intel IMVP-6/IMVP-6.5 CPUs
Description
n Supports 7-Bit IMVP-6/IMVP-6.5 VID Code and
Features
n Wide VIN Range: 4.5V to 36V Operation with
Optional Line Feedforward Compensation
n tON(MIN) < 35ns, Capable of Very Low Duty Cycle
n Temperature Compensated Inductor DCR or Sense
Resistor Output Current Monitoring
n Differential Remote Output Voltage Sensing with
Programmable Active Voltage Positioning
n Phase-Lockable Fixed Frequency: 150kHz to 550kHz
n Programmable UVLO, Preset VOUT at Boot-Up
n Programmable Slow Slew Rate Sleep State Exit
n Internal LDO for Single Supply Operation
n Overvoltage and Overcurrent Protection
n PWRGD and VRTT# Thermal Throttling Flags
n Power Optimization During Sleep and Light Load
n 38-Pin Thermally Enhanced eTSSOP and 5mm × 7mm
QFN Packages
Applications
The LTC®3816 is a single-phase synchronous step-down
DC/DC switching regulator controller that drives N-channel
power MOSFETs in a constant-frequency voltage mode
architecture. The controller’s leading edge modulation to-
pology allows extremely low output voltages and supports
a phase-lockable switching frequency up to 550kHz. The
output voltage is programmed using a 7-bit VID code.
The LTC3816 features all of the IMVP-6/IMVP-6.5 require-
ments, including start-up to a preset boot voltage, differ-
ential remote output voltage sensing with programmable
active voltage positioning, IMON output current reporting,
power optimization during sleep state, and fast or slow
slew rate sleep state exit.
Fault protection features include input undervoltage
lockout, cycle-by-cycle current limit, output overvoltage
protection, and PWRGD and overtemperature flags.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and RSENSE
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents, including 5408150, 5055767, 5481178, 6580258.
n Embedded Computing
n Mobile Computers, Internet Devices
n Navigation Displays
Typical Application
High Efficiency, Synchronous IMVP-6/ IMVP-6.5 Step-Down Controller
VCCP
1.1V
V3
3.3V
PWRGD
CLKEN#
VRTT#
RPTC
2.2nF
56Ω 1.9k 1.9k
VIN EXTVCC INTVCC
VRON
DPRSLPVR
MODE/SYNC
INTVCC
PWRGD
TG
CLKEN#
VRTT#
BOOST
VRON
DPRSLPVR
MODE/SYNC
SW
BG
RFREQ
BSOURCE
LFF LTC3816
VID0-VID6
ISENP
RPTC
ISENN
CSLEW
22pF SS
470pF
IMAX
ITCFB
10k
12k 22pF
10pF
SERVO
VFB
COMP
GND
ITC
PREIMON
IMON
VCC(SEN)
VSS(SEN)
4.7µF
0.1µF
2.55k
0.1µF
6.98k
8.25k
15nF 14k
5.1k
+
VIN
4.5V TO 36V
47µF s2 + 10µF s2
0.33µH,
1.3mΩ
NTC
+ VCC(CORE)
330µF s3
+ 10µF s20
10k
IMON
21k 15nF
3816 TA01
Efficiency and Power Loss
vs Load Current
100
90
VIN = 12V, fOSC = 400kHz
VCC(CORE) = 0.75V, VEXTVCC = 5V
80 FORCED CONTINUOUS MODE
10
9
8
70 7
60
50 EFFICIENCY
6
5
40 4
30 3
20 2
10
VIN + VEXTVCC LOSS
1
0
0.01
0.1 1
LOAD CURRENT (A)
10
0
3816 TA01b
3816f
1 page  
LTC3816
E lectrical Characteristics The l denotes the specifications which apply over the full operating
junction temperature range, otherwise
otherwise noted. (Notes 2, 3)
specifications
are
at
TA
=
25°C.
VIN
=
12V,
BSOURCE
=
EXTVCC
=
0V,
VRON
=
5V,
unless
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX
VID, DPRSLPVR, LFF Parameters
VIL(VID)
VID Input Low Threshold
VIH(VID)
VID Input High Threshold
IVID VID Input Leakage Current
VDPRSLPVR DPRSLPVR Input Threshold
ILFF LFF Pull-Up Current
VLFF LFF Input Threshold
PWRGD, CLKEN#, VRTT#
0V ≤ VVID ≤ 5V
VIMON = INTVCC (IMVP-6 Configuration)
VLFF = 0V
0.3
0.7
±1
1.6
–1
1
VPWRGD
Positive Power Good Threshold
Negative Power Good Threshold
With Respect to VID VCC(CORE)
150 175 200
–240 –270 –300
ILEAK
VOL
tPWRGD
tCLKEN#
PWRGD, CLKEN# Leakage Current
VRTT# Leakage Current
PWRGD, CLKEN# Output Low Voltage
VRTT# Output Low Voltage
PWRGD Glitch Filter
CLKEN# Falling Edge Delay
VVVPRWTRTG#D==3.V3CVLKEN# = 5V
IIOOUUTT
=
=
2mA
20mA
Power Good to Power Bad
Rising
Falling
VEdBOgOeT
Edge
to
CLKEN#
l 50
0.1
0.075
750
75
10
100
0.3
0.18
100
tCLK(PWRGD)
tVR(PWRGD)
CLKEN# to PWRGD Rising Edge Delay
VRON to PWRGD Falling Edge Delay
VRON Falling Edge
l5
10 20
100
UNITS
V
V
µA
V
µA
V
mV
mV
µA
µA
V
V
µs
µs
ms
ns
Note 1: Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. Exposure to any
Absolute Maximum Rating condition for extended periods may affect
device reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of
device pins are negative. All voltages are referenced to ground unless
otherwise specified.
Note 3: The LTC3816 is tested under pulse load conditions such that
TJ ≈ TA. The LTC3816E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. LTC3816I specifications are
guaranteed over the full –40°C to 125°C operating junction temperature
range. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance
and other environmental factors. TJ is calculated from the ambient
temperature, TA, and power dissipation, PD, according to the following
formula,
LTC3816EFE: TJ = TA + (PD • 29°C/W)
LTC3816EUHF: TJ = TA + (PD • 34°C/W)
Note 4: The dynamic input supply current is a function of the power
MOSFET gate charging (QG • fOSC). See Applications Information for
more information.
Note 5: The LTC3816 is measured in a feedback loop that adjusts
VCC(SEN) – VSS(SEN) to achieve a specified COMP pin voltage. The AITC
amplifier is configured as an inverter with gain = –1.
Note 6: Guaranteed by design, not subject to test.
Note 7: On-resistance limit is guaranteed by design and correlation
with statistical process controls.
Note 8: The LTC3816 includes overtemperature protection that is
intended to protect the device during momentary overload conditions.
The maximum rated junction temperature will be exceeded when this
protection is active. Continuous operation above the specified absolute
maximum operating junction temperature may impair device reliability
or permanently damage the device.
3816f
5 Page 
LTC3816
Pin Functions (eTSSOP/QFN)
ISENN (Pin 1/Pin 36): Current Sense Negative Input. Con-
nect this pin to the negative terminal of the current sense
resistor or the negative terminal of the inductor DCR
lowpass filter.
ITCFB (Pin 2/Pin 37): Inductor DCR Temperature Compen-
sation Amplifer Feedback Input. To derive the temperature
compensated voltage dropped across the inductor DCR,
connect a resistor from the SW node to this pin. An NTC
network, in parallel with a capacitor, forms the feedback
path of this amplifier. For applications that use a discrete
resistor for current sensing, replace the NTC network
with a resistor.
ITC (Pin 3/Pin 38): Inductor DCR Temperature Compen-
sation Amplifer Output. The IMON circuitry and the error
amplifier obtain the temperature compensated DCR voltage
through this amplifier.
PREIMON (Pin 4/Pin 1): IMON Current Output Setting.
PREIMON is servoed to the ISENN potential. A resistor from
PREIMON to ITC sets the IMONoutput current. For the IMVP-6
configuration, connect this pin to INTVCC.
IMON(Pin 5/Pin 2): IMVP-6/IMVP-6.5 Configuration Selec-
tion and Output Current Monitor. Connect this pin to INTVCC
to select the IMVP-6 configuration. At start-up, the switcher
VOUT is ramped to 1.2V (VBOOT). In deeper sleep mode,
the controller enables the slow VOUT slew rate. Connect a
resistor to VSS(SEN) to select the IMVP-6.5 configuration.
In this case, VBOOT equals 1.1V, slow slew rate is disabled
and the IMON current source is proportional to the load. In
the IMVP-6.5 configuration, this pin is internally clamped
to 1.1V with respect to the VSS(SEN) pin.
RPTC (Pin 6/Pin 3): Nonlinear PTC Thermistor Input.
Connect to a nonlinear PTC thermistor for MOSFET or
inductor temperature sensing. This pin is pulled up by a
100µA current source. If the potential at RPTC is higher
than 0.47V, thermal flag VRTT# is pulled low. RPTC is
sensitive to noise pickup. Avoid coupling high frequency
switching signals to this pin. If required, bypass this
pin with a capacitor to GND.
VRON (Pin 7/Pin 4): Voltage Regulator Enable Input. The
VRON pin power-up threshold is 1.2V. When forced below
0.65V, a power-down sequence is initiated where the
VCC(CORE) output is ramped down near 0V before the IC
is put into a low current shutdown mode. The VRON pin
has an internal 1µA pull-up current.
VSS(SEN) (Pin 8/Pin 5): Processor VCC(CORE) Negative
Terminal Voltage Sense. Negative input of the differential
sense amplifier. Connect to the processor VSS(SEN) pin.
VCC(SEN) (Pin 9/Pin 6): Processor VCC(CORE) Positive
Terminal Voltage Sense. Positive input of the differential
sense amplifier. Connect to the processor VCC(SEN) pin.
SERVO (Pin 10/Pin 7): Error Amplifier AC Input. The
controller servos the switcher output voltage to the VID
DAC voltage through the error amplifier.
VFB (Pin 11/Pin 8): Error Amplifier Negative Input Pin.
VFB is servoed to 1.3V.
COMP (Pin 12/Pin 9): Error Amplifier Output. The COMP
pin is connected directly to the error amplifier output and
the input of the line feedforward circuit. Use an RC network
between the COMP pin and the VFB pin to compensate
the feedback loop for stability and optimum transient
response.
SS (Pin 13/Pin 10): Soft-Start Input. The SS pin has an
internal 1µA current source pull-up. A capacitor connected
to this pin controls the output voltage start-up. SS is
forced low if VRON or PWRGD is low, or if an overvoltage
or overcurrent fault occurs. If the potential at SS is less
than 0.3V, the IMAX sourcing current is reduced to 2.5µA
and the current limit threshold is reduced to 25% of its
nominal value.
DPRSLPVR (Pin 14/Pin 11): Deeper Sleep Mode. For the
IMVP-6 configuration, 25µs after DPRSLPVR is asserted
high, the controller enables the VOUT slow slew rate tran-
sition. To disable slow slew rate mode, force DPRSLPVR
low. Upon power-up, the DPRSLPVR input is ignored until
PWRGD is asserted.
3816f
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC3816.PDF ] | |
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