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PDF DK2052 Data sheet ( Hoja de datos )

Número de pieza DK2052
Descripción HIGH PERFORMANCE WIDEBAND RF PLL/VCO
Fabricantes RF Micro Devices 
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RF2052
HIGH PERFORMANCE WIDEBAND RF
PLL/VCO WITH INTEGRATED RF MIXER
Package: QFN, 32-Pin, 5mmx5mm
Features
30MHz to 2.5GHz Frequency
Range
Fractional-N Synthesizer
Very Fine Frequency Resolution
1.5Hz for 26MHz Reference
Low Phase Noise VCO
On-Chip Crystal-Sustaining
Circuit With Programmable
Loading Capacitors
High-Linearity RF Mixer
Integrated LO Buffer
Mixer Input IP3 +18dBm
Mixer Bias Adjustable for Low
Power Operation
2.7V to 3.6V Power Supply
Low Current Consumption
55mA to 75mA at 3V
3-Wire Serial Interface
Applications
CATV Head-Ends
Digital TV Up/Down Converters
Digital TV Repeaters
Multi-Dwelling Units
Cellular Repeaters
Frequency Band Shifters
UHF/VHF Radios
Software Defined Radios
Satellite Communications
Super-Heterodyne Radios
BPSK Modulator
VCO
LO
divider
Synth
Frac-N
sequence
generator
Charge
pump
N divider
Phase /
freq
detector
Mixer
Ref
divider
Functional Block Diagram
Product Description
The RF2052 is a low power, high performance, wideband RF frequency conversion
chip with integrated local oscillator (LO) generation and RF mixer. The RF synthe-
sizer includes an integrated fractional-N phase locked loop with voltage controlled
oscillators (VCOs) and dividers to produce a low-phase noise LO signal with a very
fine frequency resolution. The buffered LO output drives the built-in RF mixer which
converts the signal into the required frequency band. The mixer bias current can be
programmed dependent on the required performance and available supply current.
The LO generation blocks have been designed to continuously cover the frequency
range from 300MHz to 2400MHz. The RF mixer is very broad band and operates
from 30MHz to 2500MHz at the input and output, enabling both up and down con-
version. An external crystal of between 10MHz and 52MHz or an external reference
source of between 10MHz and 104MHz can be used with the RF2052 to accom-
modate a variety of reference frequency options.
All on-chip registers are controlled through a simple three-wire serial interface. The
RF2052 is designed for 2.7V to 3.6V operation for compatibility with portable, bat-
tery powered devices. It is available in a plastic 32-pin, 5mmx5mm QFN package.
Optimum Technology Matching® Applied
GaAs HBT
GaAs MESFET
InGaP HBT
SiGe BiCMOS
Si BiCMOS
SiGe HBT
GaAs pHEMT
Si CMOS
Si BJT
GaN HEMT
RF MEMS
LDMOS
DS140110
RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trade-
mark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2006, RF Micro Devices, Inc.
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
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DK2052 pdf
RF2052
Parameter
Mixer, cont.
IIP3
Low Current Setting
High Linearity Setting
Pin1dB
Low Current Setting
High Linearity Setting
RF and IF Port Frequency Range
Mixer Input Return Loss
Voltage Controlled Oscillator
Open Loop Phase Noise at 1MHz
Offset
2GHz LO Frequency
1GHz LO Frequency
500MHz LO Frequency
Reference Oscillator
Xtal Frequency
External Reference Frequency
Reference Divider Ratio
External Reference Input Level
Local Oscillator
Synthesizer Output Frequency
Phase Detector Frequency
Closed Loop Phase-Noise at
10kHz Offset
2GHz LO Frequency
1GHz LO Frequency
500MHz LO Frequency
Specification
Min. Typ. Max.
+10
+18
+2
+12
30 2500
10
-130
-135
-140
10 52
10 104
17
500 800 1500
300 2400
52
-90
-95
-102
Unit Condition
dBm
dBm
dBm
dBm
MHz
dB 100differential
dBc/Hz
dBc/Hz
dBc/Hz
MHz
MHz
mVP-P
AC-coupled
MHz
MHz
dBc/Hz
dBc/Hz
dBc/Hz
Dependant on VCO 3 external inductor. After
LO dividers.
26MHz phase detector frequency
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
5 of 37

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DK2052 arduino
RF2052
Fractional-N PLL
The IC contains a charge-pump based fractional-N phase locked loop (PLL) for controlling the three VCOs. The PLL includes
automatic calibration systems to counteract the effects of process and environmental variations, ensuring repeatable lock-
time and noise performance. The PLL is intended to use a reference frequency signal of 10MHz to 104MHz. A reference
divider (divide by 1 to divide by 7) is supplied and should be programmed to limit the frequency at the phase detector to a max-
imum of 52MHz. The reference divider bypass is controlled by bit CLK DIV_BYP, set low to enable the reference divider and set
high for divider bypass (divide by 1). The remaining three bits CLK DIV<15:13> set the reference divider value, divide by 2
(010) to 7 (111) when the reference divider is enabled.
Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the
label PLL2. For the RF2052 the default programming bank is PLL2, selected by setting the MODE pin high.
The PLL will lock the VCO to the frequency FVCO according to:
FVCO =NEFF*FOSC/R
where NEFF is the programmed fractional N divider value, FOSC is the reference input frequency, and R is the programmed R
divider value (1 to 7).
The N divider is a fractional divider, containing a dual-modulus prescaler and a digitally spur-compensated fractional sequence
generator to allow fine frequency steps. The N divider is programmed using the N and NUM bits as follows:
First determine the desired, effective N divider value, NEFF:
NEFF = FVCO*R/FOSC
N(9:0) should be set to the integer part of NEFF. NUM should be set to the fractional part of NEFF multiplied by 224=16777216.
Example: VCO1 operating at 2220MHz, 23.92MHz reference frequency, the desired effective divider value is:
NEFF=FVCO *R / FOSC=2220 *1 / 23.92=92.80936454849.
The N value is set to 92, equal to the integer part of NEFF, and the NUM value is set to the fractional portion of NEFF multiplied
by 224:
NUM=0.80936454895 * 224=13,578,884.
Converting N and NUM into binary results in the following:
N=0 0101 1100
NUM=1100 1111 0011 0010 1000 0100
So the registers would be programmed:
P2_N=0 0101 1100
P2_NUM_MSB=1100 1111 0011 0010
P2_NUM_LSB=1000 0100
The maximum NEFF is 511, and the minimum NEFF is 15, when in fractional mode. The minimum step size is FOSC/R*224. Thus
for a 23.92MHz reference, the frequency step size would be 1.4Hz. The minimum reference frequency that could be used to
program a frequency of 2400MHz (using VCO1) is 2400/511, 4.697MHz (approx).
DS140110
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or [email protected].
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