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PDF PCT25VF032B Data sheet ( Hoja de datos )
| Número de pieza | PCT25VF032B | |
| Descripción | 32 Mbit SPI Serial Flash | |
| Fabricantes | PCT | |
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FEATURES:
32 Mbit SPI Serial Flash
PCT25VF032B
SST25VF032B32Mb Serial Peripheral Interface (SPI) flash memory
Data Sheet
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
– 80 MHz Max
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Read Current: 10 mA (typical)
– Standby Current: 5 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 7 µs (typical)
• Auto Address Increment (AAI) Word Programming
– Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
– Write protection through Block-Protection bits in
status register
• Temperature Range
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC (200 mils)
– 8-contact WSON (5 X 6 mm)
• All devices are RoHS compliant
PRODUCT DESCRIPTION
The PCT 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ultimately
lowers total system costs. PCT25VF032B SPI serial flash
memories are manufactured with SST’s proprietary, high-
performance CMOS SuperFlash technology. The split-gate
cell design and thick-oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches.
The PCT25VF032B devices significantly improve perfor-
mance and reliability, while lowering power consumption.
The devices write (Program or Erase) with a single power
supply of 2.7-3.6V for PCT25VF032B. The total energy
consumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed during
any Erase or Program operation is less than alternative
flash memory technologies.
The PCT25VF032B device is offered in 8-lead SOIC (200
mils) and 8-contact WSON packages. See Figure 2 for pin
assignments.
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32 Mbit SPI Serial Flash
3&T25VF032B
Hold Operation
The HOLD# pin is used to pause a serial sequence using
the SPI flash memory, but without resetting the clocking
sequence. To activate the HOLD# mode, CE# must be in
active low state. The HOLD# mode begins when the SCK
active low state coincides with the falling edge of the
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD# signal does not
Data Sheet
coincide with the SCK active low state, then the device
exits from Hold mode when the SCK next reaches the
active low state. See Figure 4 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be VIL or VIH.
If CE# is driven high during a Hold condition, the device
returns to Standby mode. As long as HOLD# signal is low,
the memory remains in the Hold condition. To resume
communication with the device, HOLD# must be driven
active high, and CE# must be driven active low. See Figure
4 for Hold timing.
SCK
HOLD#
Active
Hold
Active
Hold
Active
1327 F05.0
FIGURE 4: Hold Condition Waveform
Write Protection
3&T25VF032B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-down
function of the status register. The Block-Protection bits
(BP3, BP2, BP1, BP0, and BPL) in the status register pro-
vide Write protection to the memory array and the status
register. See Table 4 for the Block-Protection description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down func-
tion of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 2). When WP# is high, the lock-down func-
tion of the BPL bit is disabled.
TABLE 2: Conditions to execute Write-Status-
Register (WRSR) Instruction
WP#
L
L
H
BPL
1
0
X
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
T2.0 1327
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32 Mbit SPI Serial Flash
PCT25VF032B
Auto Address Increment (AAI) Word-Program
The AAI program instruction allows multiple bytes of data to
be programmed without re-issuing the next sequential
address location. This feature decreases total program-
ming time when multiple bytes or entire memory array is to
be programmed. An AAI Word program instruction pointing
to a protected memory area will be ignored. The selected
address range must be in the erased state (FFH) when ini-
tiating an AAI Word Program operation. While within AAI
Word Programming sequence, the only valid instructions
are AAI Word (ADH), RDSR (05H), or WRDI (04H). Users
have three options to determine the completion of each
AAI Word program cycle: hardware detection by reading
the Serial Output, software detection by polling the BUSY
bit in the software status register or wait TBP. Refer to End-
Of-Write Detection section for details.
Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. The AAI Word Program
instruction is initiated by executing an 8-bit command,
ADH, followed by address bits [A23-A0]. Following the
addresses, two bytes of data is input sequentially, each one
from MSB (Bit 7) to LSB (Bit 0). The first byte of data (D0)
will be programmed into the initial address [A23-A1] with A0
= 0, the second byte of Data (D1) will be programmed into
the initial address [A23-A1] with A0 = 1. CE# must be driven
high before the AAI Word Program instruction is executed.
The user must check the BUSY status before entering the
next valid command. Once the device indicates it is no
longer busy, data for the next two sequential addresses
may be programmed and so on. When the last desired
byte had been entered, check the busy status using the
hardware method or the RDSR instruction and execute the
Write-Disable (WRDI) instruction, 04H, to terminate AAI.
Check the busy status after WRDI to determine if the
device is ready for any command. See Figures 10 and 11
for AAI Word programming sequence.
There is no wrap mode during AAI programming; once the
highest unprotected memory address is reached, the
device will exit AAI operation and reset the Write-Enable-
Latch bit (WEL = 0) and the AAI bit (AAI = 0).
End-of-Write Detection
There are three methods to determine completion of a pro-
gram cycle during AAI Word programming: hardware
detection by reading the Serial Output, software detection
by polling the BUSY bit in the Software Status Register or
wait TBP. The hardware end-of-write detection method is
described in the section below.
Data Sheet
Hardware End-of-Write Detection
The hardware end-of-write detection method eliminates the
overhead of polling the Busy bit in the Software Status
Register during an AAI Word program operation. The 8-bit
command, 70H, configures the Serial Output (SO) pin to
indicate Flash Busy status during AAI Word programming,
as shown in Figure 8. The 8-bit command, 70H, must be
executed prior to executing an AAI Word-Program instruc-
tion. Once an internal programming operation begins,
asserting CE# will immediately drive the status of the inter-
nal flash status on the SO pin. A ‘0’ indicates the device is
busy and a ‘1’ indicates the device is ready for the next
instruction. De-asserting CE# will return the SO pin to tri-
state.
The 8-bit command, 80H, prevents the Serial Output (SO)
pin from outputting Busy status during AAI-Word-program
operation and re-configures SO as an output pin. The
device can only accept the 80H command when the device
is not in AAI mode. Once SO is an output pin, in AAI mode
the device can accept both RDSR instruction for polling
and Software Status Register data outputs through the SO
pin. This is shown in Figure 9.
CE#
MODE 3
SCK MODE 0
0 1 23456 7
SI 70
MSB
SO HIGH IMPEDANCE
1327 F09.0
FIGURE 8: Enable SO as Hardware RY/BY#
during AAI Programming
CE#
MODE 3
SCK MODE 0
0 1 23456 7
SI 80
MSB
SO HIGH IMPEDANCE
1327 F10.0
FIGURE 9: Disable SO as Hardware RY/BY#
during AAI Programming
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| PDF Descargar | [ Datasheet PCT25VF032B.PDF ] | |
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