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PDF M24C16-A125 Data sheet ( Hoja de datos )
| Número de pieza | M24C16-A125 | |
| Descripción | Automotive 16-Kbit serial I2C bus EEPROM | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M24C16-A125
Automotive 16-Kbit serial I²C bus EEPROM with 1 MHz clock
TSSOP8 (DW)
169 mil width
SO8 (MN)
150 mil width
WFDFPN8 (MF)
2 x 3 mm
Datasheet - production data
Features
• Compatible with all I2C bus modes
– 1 MHz
– 400 kHz
– 100 kHz
• Memory array
– 16 Kbits (2 Kbytes) of EEPROM
– Page size: 16 bytes
– Additional Write lockable page
(Identification page)
• Extended temperature and voltage ranges
– -40 °C to 125 °C; 1.8 V to 5.5 V
• Schmitt trigger inputs for noise filtering
• Short Write cycle time
– Byte Write within 4 ms
– Page Write within 4 ms
• Write cycle endurance
– 4 million Write cycles at 25 °C
– 1.2 million Write cycles at 85 °C
– 600 k Write cycles at 125 °C
• Data retention
– 50 years at 125 °C
– 100 years at 25 °C
• ESD Protection (Human Body Model)
– 4000 V
• Packages
– RoHS compliant and halogen-free
(ECOPACK2®)
January 2015
This is information on a product in full production.
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1 page  
M24C16-A125
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C
bus at maximum frequency fC =
Maximum Rbus value versus bus
400 kHz
parasitic
..........
capacitance
.....
Cbus)
.....
for an
...
I2C
.
.
.
.
.
.
.
.
.
.
.
.
.
.
28
bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 30
SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 31
WFDFPN8 (MLP8) – 8-lead thin fine pitch dual flat package no lead
2 x 3 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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M24C16-A125
Device operation
3.5 Device addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, as
shown in Table 2 (on Serial Data (SDA), most significant bit first).
Table 2. Device select code
Device type identifier (1)
Chip Enable address
b7 b6 b5 b4 b3 b2 b1
When accessing the
memory
1
0
1
0 A10 A9 A8
When accessing the
identification page
1
0
1
1
X
X
X
1. The most significant bit, b7, is sent first.
RW
b0
RW
RW
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding memory device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the memory device does not
match the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 3. Significant address bits
Memory
(Device type identifier = 1010b)
Identification page
(Device type identifier = 1011b)
Random
Address Read
b3 (1)
b2 (1)
b1 (1)
A10
A9
A8
Write
A10
A9
A8
Read
Write
Lock
Identification Identification Identification Read lock status
page
page
page
XXX
XXX
XXX
b7 A7
A7 0
b6 A6
A6 X
b5 A5
A5 X
b4 A4
A4 X
b3 A3
A3 A3
b2 A2
A2 A2
b1 A1
A1 A1
b0 A0
A0 A0
1. Address bits defined inside the DeviceSelect code (see Table 2).
0
X
X
X
A3
A2
A1
A0
1
X
X see Section 4.2.5
X
X
X
X
X
Note:
A: significant address bit.
X: bit is Don’t Care.
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| PDF Descargar | [ Datasheet M24C16-A125.PDF ] | |
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