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PDF M24128S-FCV Data sheet ( Hoja de datos )
| Número de pieza | M24128S-FCV | |
| Descripción | 128-Kbit serial I2C bus EEPROM 4 balls CSP | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M24128S-FCU
M24128S-FCV
128-Kbit serial I²C bus EEPROM 4 balls CSP
WLCSP (CU)
WLCSP (CV)
Datasheet - production data
Features
• Compatible with the 400 kHz I²C protocol
• High speed 1MHz transfer rate
• Memory array:
– 128 Kbit (16 Kbyte) of EEPROM
– Page size: 32 byte
• Supply voltage range:
– 1.7 V to 5.5 V
• Operating temperature range
– VCC = 1.7 V to 5.5V over -40°C / +85°C
– VCC = 1.6 V to 5.5V over 0°C / +85°C
• Write
– Byte Write within 5 ms
– Page Write within 5 ms
• Random and sequential Read modes
• Software Write protect
– Upper quarter memory array
– Upper half memory array
– Upper 3/4 memory array
– Whole memory array
• ESD protection
– Human Body Model: 4 kV
• More than 4 million Write cycles
• More than 200-years data retention
• Package
– WLCSP, RoHS and Halogen free compliant
(ECOPACK2®)
November 2015
This is information on a product in full production.
DocID025717 Rev 7
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M24128S-FCU M24128S-FCV
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4-bump WLCSP connections
(top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write mode sequence (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write mode sequence (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
aMnaxI2imC ubmusRabtums vaaxliumeuvmerfsreuqsubeunscypafCra=si4tic00cakpHazci.ta.n.c.e.
(Cbus) for
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Maximum
for an I2C
Rbus value versus bus parasitic
bus at high clock frequency . . .
capacitance
..........
(Cbus)
......
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AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Ultra Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Ultra Thin WLCSP-BSC - 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Thin WLCSP- 4-bump, 0.833 x 0.833 mm, wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Ultra ultra Thin WLCSP-BSC - 4-bump, 0.851 x 0.851 mm, wafer level chip
scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Ultra ultra thin WLCSP- 4-bump, 0.851 x 0.851 mm, wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Ultra ultra thin WLCSP- 4-bump, 0.851 x 0.851 mm, wafer level chip
scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DocID025717 Rev 7
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M24128S-FCU M24128S-FCV
4 Device operation
Device operation
The device supports the I2C protocol. This is summarized in Figure 4. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
Figure 4. I2C bus protocol
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DocID025717 Rev 7
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| M24128S-FCU | 128-Kbit serial I2C bus EEPROM 4 balls CSP | STMicroelectronics |
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