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PDF L9959 Data sheet ( Hoja de datos )
| Número de pieza | L9959 | |
| Descripción | Single and dual PMOS high-side H-bridge | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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L9959
Single and dual PMOS high-side H-bridge
Datasheet - production data
'!0'03
PowerSSO24
'!0'03
PowerSSO36
Current-monitoring with current feedback
output signal CF
SPI-interface for configuration and diagnosis
Error history in second diagnosis register
Two independent enable pins: "/ABE" and
"DIS"
Control of power stages by SPI or two input
signals, PWM and DIR (configurable via SPI)
Logic levels 5 V compatible
Conformity to improved EMC requirements due
to smart H-bridge switching
Features
Full path RDSON less than 540 mΩ
Continuous load current > 3 A
Operating battery supply voltage 5 V to 28 V
Operating VDD supply voltage 4.5 V to 5.5 V
All ECU internal pins can withstand up to 18 V
Output switching frequency up to 11 kHz
Monitoring of VDD supply voltage
SPI programmable output current limitation
from 5 A to 8.6 A (in 3 steps)
Over temperature and short circuit protection
Full diagnosis capability
Fast switch-off open-drain input/output
Description
L9959S/L9959U and L9959T are single and dual
integrated H-bridges for resistive and inductive
loads featuring output current direction and
supervising functions.
The PowerSSO24 houses one full H-Bridge, while
the PowerSSO36 houses both two H-Bridges that
can work in parallel, through independent input
driving commands, and one full H-bridge, by
improving PCB footprint design versus different
target applications.
Target application ranges from throttle control
actuators to exhaust gas recirculation control
valves in automotive domain to a more general
use to drive DC and Stepper motors.
Order code
L9959S-TR-D
L9959T-TR-D
L9959U-TR-D
Table 1. Device summary
Package
PowerSSO24
PowerSSO36
PowerSSO36
Packing
Tape & Reel
Tape & Reel
Tape & Reel
October 2015
This is information on a product in full production.
DocID027540 Rev 2
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1 page  
L9959
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PSSO24 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSSO36 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSSO36 (Single version) pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Output delay times (e.g. low-side output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output disable and enable time (/ABE Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output disable and enable time (DIS Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPI timing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PWM mode current flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PWM mode output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DIR-change (current is changing its direction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DIR-change current flow phase 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DIR-change output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Current feedback and current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Current limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Temperature dependent current reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Current limiting and short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
PowerSSO-24 (exposed pad) package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PowerSSO-36 (exposed pad) package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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L9959
Pins description
Table 3. L9959T (Two H-Bridge drivers in one package) PSSO36 pin-out (continued)
Pin Symbol
Function
Current Proportional Feedback output:
25
CF2
The CF pin provides in conjunction with an external resistor an output current, which is
proportional to the H-Bridge current. CF1 belongs to OUT11 and OUT12, CF2 to OUT21
and OUT22.
Bidirectional Ability/Enable Pin 2:
26 /ABE2 Open-Drain Output, which is pulled low in case of VDD over- and under-voltage. If the input
is pulled to low, all output stages are switched off. /ABE2 belongs to chip 2.
27
30
31, 32
33
34
GNDABE2
VDD1(2)
VS1(3)
DIS1
DIR1
Sense Ground for VDD monitoring
VDD Supply: 5V Supply.
Power supply voltage for power stage outputs (external reverse protection required):
Important: For the capability of driving the full current at the outputs all pins of VS must be
externally connected.
Disable input 1:
DIS1 switches OUT11 and OUT12 to tristate
Direction input 1:
DIR1 pin controls the switch direction of OUT11 and OUT12.
35
PWM1
PWM input 1:
PWM1 input switches OUT11 and OUT12.
Bridge output 11, 12, 21, and 22:
36 OUT12 The bridge outputs are built of a high-side p-channel and a low-side N-channel transistor.
The bridge outputs of chip 1 are OUT11 and OUT12, of chip 2 OUT21 and OUT22.
EP AGND(4) Exposed PAD: connected to AGND
1. Pins 1 is referred to die 1, whereas 19 is referred to die 2.
2. Pins 12 is referred to die 2, whereas 30 is referred to die 1.
3. Pins 13 and 14 are referred to die 2, whereas pins 31 and 32 are referred to die1.
4. Pins 10 is referred to die 2, whereas 28 is referred to die 1.
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet L9959.PDF ] | |
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