|
|
PDF L6751B Data sheet ( Hoja de datos )
| Número de pieza | L6751B | |
| Descripción | Digitally controlled dual PWM | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de L6751B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
L6751B
Digitally controlled dual PWM for Intel VR12 and AMD SVI
Features
■ VR12 compliant with 25 MHz SVID bus rev1.5
– SerialVID with programmable IMAX,
TMAX, VBOOT, ADDRESS
■ AMD SVI compliant
■ Second generation LTB Technology®
■ Flexible driver/DrMOS support
■ JMode support
■ Fully configurable through PMBus™
■ Dual controller:
– up to 6 phases for CORE and memory
– 1 phase for graphics (GFX), system agent
(VSA) or Northbridge (VDDNB)
■ Single NTC design for TM, LL and Imon
thermal compensation (for each section)
■ VFDE and GDC - gate drive control for
efficiency optimization
■ DPM - dynamic phase management
■ Dual remote sense; 0.5% Vout accuracy
■ Full-differential current sense across DCR
■ AVP - adaptive voltage positioning
■ Dual independent adjustable oscillator
■ Dual current monitor
■ Pre-biased output management
■ Average and per-phase OC protection
■ OV, UV and FB disconnection protection
■ Dual VR_RDY
■ VFQFPN68 8x8 mm package
Applications
■ High-current VRM / VRD for desktop / server /
workstation Intel / AMD CPUs
■ DDR3 memory supply
Datasheet − production data
QFN68 8x8 mm
Description
The L6751B is a universal digitally controlled dual
PWM DC-DC designed to power Intel’s VR12 and
AMD SVI processors and memories: all required
parameters are programmable through dedicated
pinstrapping and PMBus interface.
The device features up to 6-phase programmable
operation for the multi-phase section and a single-
phase with independent control loops. When
configured for memory supply, single-phase
(VTT) reference is always tracking multi-phases
(VDDQ) scaled by a factor of 2. The L6751B
supports power state transitions featuring VFDE,
programmable DPM and GDC maintaining the
best efficiency over all loading conditions without
compromising transient response. The device
assures fast and independent protection against
load overcurrent, under/overvoltage and feedback
disconnections.
The device is available in VFQFPN68 8x8 mm
package.
Table 1. Device summary
Order code
Package
L6751B
L6751BTR
VFQFPN68 8x8 mm
Packaging
Tray
Tape and reel
December 2012
This is information on a product in full production.
Doc ID 024028 Rev 1
1/58
www.st.com
58
1 page  
L6751B
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Typical 6-phase application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
L6751B pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
JMode: voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Current reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SLESS startup: enabled (left) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
LSLESS startup: disabled (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DVID optimization circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Thermal monitor connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Output current vs. switching frequency in PSK mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Efficiency performance with and without enhancements (DPM, GDC). . . . . . . . . . . . . . . . 44
ROSC vs. FSW per phase (ROSC to GND - left; ROSC to 3.3 V - right) . . . . . . . . . . . . . . . . 45
Equivalent control loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Control loop bode diagram and fine tuning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Device initialization: PMBus controlling Vout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
L6751B VFQFPN68 8x8 mm drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Doc ID 024028 Rev 1
5/58
5 Page 
L6751B
Pin description and connection diagram
Table 2.
Pin#
27
28
29
Pin description (continued)
Name Type
Function
SCSP
A
SCSN
A
SIMON
A
Single-phase section current senses positive input.
Connect through an R-C filter to the phase-side of the channel 1 inductor.
Single-phase section current senses negative input.
Connect through an Rg resistor to the output-side of the channel inductor.
Filter the output-side of Rg with 100 nF (typ.) to GND.
Current monitor output.
A current proportional to the single-phase current is sourced from this pin.
Connect through a resistor RSIMON to GND.
When the pin voltage reaches 1.55 V, overcurrent protection is set and the
IC latches. Filtering through CSIMON to GND allows the delay for OC
intervention to be controlled.
30 DPM4-6
A
Connect a resistor divider to GND/VCC5 in order to define the DPM and
GDC strategies. See Table 11 and Table 12 for details.
31 SRGND
A
Remote buffer ground sense.
Connect to the negative side of the single-phase load to perform remote
sense.
32 DPM1-3
A
33 SFBR
A
34 SVSEN
A
35 SFB
A
36 SCOMP
A
Connect a resistor divider to GND/VCC5 in order to define the DPM and
GDC strategies. See Table 11 and Table 12 for details.
Remote buffer positive sense.
Connect to the positive side of the single-phase load to perform remote
sense.
Remote buffer output.
Output voltage monitor, manages OV and UV protection.
Connect with a resistor RSFB // (RSI - CSI) to SFB.
Error amplifier inverting input.
Connect with a resistor RSFB // (RSI - CSI) to SVSEN and with an (RSF -
CSF)// CSH to SCOMP.
Error amplifier output.
Connect with an (RSF - CSF)// CSH to SFB. The device cannot be disabled
by pulling low this pin.
Doc ID 024028 Rev 1
11/58
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet L6751B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| L6751B | Digitally controlled dual PWM | STMicroelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |