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PDF USB3370 Data sheet ( Hoja de datos )
| Número de pieza | USB3370 | |
| Descripción | Enhanced Single Supply Hi-Speed USB ULPI Transceiver | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de USB3370 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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USB3370
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Highlights
• USB-IF Battery Charging 1.1 Specification Com-
pliant
• Link Power Management (LPM) Specification
Compliant
• Integrated ESD protection circuits
- Up to ±25kV IEC Air Discharge without exter-
nal devices
• Over-Voltage Protection circuit (OVP) protects the
VBUS pin from continuous DC voltages up to 30V
• Microchip RapidCharge Anywhere™ Provides:
- 3-times the charging current through a USB
port over traditional solutions
- USB-IF Battery Charging 1.1 compliance to
any portable device
- Charging current up to 1.5Amps via compati-
ble USB host or dedicated charger
- Dedicated Charging Port (DCP), Charging
(CDP) & Standard (SDP) Downstream Port
support
• flexPWR® Technology
- Extremely low current design ideal for battery
powered applications
- “Sleep” mode tri-states all ULPI pins and
places the part in a low current state
- 1.8V to 3.3V IO Voltage
• Single Power Supply Operation
- Integrated 1.8V regulator
- Integrated 3.3V regulator
- 100mV dropout voltage
• PHYBoost
- Programmable USB transceiver drive
strength for recovering signal integrity
• VariSenseTM
- Programmable USB receiver sensitivity
• “Wrapper-less” design for optimal timing perfor-
mance and design ease
- Low Latency Hi-Speed Receiver (43 Hi-
Speed clocks Max) allows use of legacy
UTMI Links with a ULPI bridge
• External Reference Clock operation available
- 19.2MHz Reference Clock needed
- ULPI Clock Input Mode (60MHz sourced by
Link)
- 0 to 3.6V input drive tolerant
- Able to accept “noisy” clock sources as refer-
ence to internal, low-jitter PLL
- Crystal support available
• Smart detection circuits allow identification of
USB charger, headset, or data cable insertion
• Includes full support for the optional On-The-Go
(OTG) protocol detailed in the On-The-Go Sup-
plement Revision 2.0 specification
• Supports the OTG Host Negotiation Protocol
(HNP) and Session Request Protocol (SRP)
• UART mode for non-USB serial data transfers
• Internal 5V cable short-circuit protection of ID, DP
and DM lines to VBUS or ground
• Industrial Operating Temperature -40°C to +85°C
• 32 pin, QFN RoHS Compliant package
(5 x 5x 0.90 mm height)
Applications
The USB3370 is the solution of choice for any applica-
tion where a Hi-Speed USB connection is desired and
when board space, power, and interface pins must be
minimized.
• Cell Phones
• PDAs
• MP3 Players
• GPS Personal Navigation
• Scanners
• External Hard Drives
• Digital Still and Video Cameras
• Portable Media Players
• Entertainment Devices
• Printers
• Set Top Boxes
• Video Record/Playback Systems
• IP and Video Phones
• Gaming Consoles
2012 - 2015 Microchip Technology Inc.
DS00001915B-page 1
1 page  
FIGURE 1-1:
BLOCK DIAGRAM USB3370
USB3370
EXTVBUS
CPEN_N
VBUS
ID
DP
DM
OVP
BC 1.1
OTG
Hi-Speed
USB
Transceiver
Low Jitter
Integrated
PLL
ULPI
Registers
and State
Machine
BIAS
RBIAS
Integrated
Power
Management
ULPI
Interface
RESETB
VBAT
VDD33
VDD18
VDDIO
STP
NXT
DIR
CLKOUT
DATA[7:0]
The USB3370 includes an integrated 3.3V LDO regulator that is used to generate 3.3V from power applied to the VBAT
pin. The voltage on the VBAT pin can range from 3.0 to 5.5V. The regulator dropout voltage is less than 100mV which
allows the PHY to continue USB signaling when the voltage on VBAT drops to 3.0V. The USB transceiver will continue
to operate at lower voltages, although some parameters may be outside the limits of the USB specifications. The VBAT
and VDD33 pins should never be connected together.
In USB UART mode, the USB3370 DP and DM pins are redefined to enable pass-through of asynchronous serial data.
The USB3370 will enter UART mode when programmed, as described in Section 6.7.1.
1.1 Reference Documents
UTMI+ Low Pin Interface (ULPI) Specification, Rev. 1.1
Universal Serial Bus Specification, Revision 2.0
On-The-Go Supplement to the USB2.0 Specification, Rev. 1.3
On-The-Go Supplement to the USB2.0 Specification, Rev. 2.0
USB Battery Charging Specification, Rev. 1.1
2012 - 2015 Microchip Technology Inc.
DS00001915B-page 5
5 Page 
USB3370
4.3 ULPI Interface Timing
TABLE 4-3: ULPI INTERFACE TIMING
Parameter
Symbol
Conditions
MIN MAX Units
60MHz ULPI Output Clock Note 4-6
Setup time (STP, data in)
Hold time (STP, data in)
Output delay (control out, 8-bit data out)
TSC, TSD
THC, THD
TDC, TDD
Model-specific REFCLK
Model-specific REFCLK
Model-specific REFCLK
5.0
0.0
1.5
6
ns
ns
ns
60MHz ULPI Input Clock
Setup time (STP, data in)
Hold time (STP, data in)
Output delay (control out, 8-bit data out)
TSC, TSD
THC, THD
TDC, TDD
60MHz REFCLK
60MHz REFCLK
60Mhz REFCLK
3 ns
0 ns
0.5 6.0 ns
Note: CLoad = 10pF.
Note 4-6 REFCLK does not need to be aligned in any way to the ULPI signals.
4.4 Digital IO Pins
TABLE 4-4: DIGITAL IO CHARACTERISTICS: RESETB, STP, DIR, NXT, DATA[7:0], AND REFCLK
PINS
Parameter
Low-Level Input Voltage
High-Level Input Voltage
High-Level Input Voltage
REFCLK and RESETB
Low-Level Output Voltage
High-Level Output Voltage
Output rise time
Output fall time
Input Leakage Current
Pin Capacitance
STP pull-up resistance
DATA[7:0] pull-down
resistance
CLKOUT External Drive
Symbol
VIL
VIH
VIH_REF
VOL
VOH
TIORISE
TIOFALL
ILI
Cpin
RSTP
RDATA_PD
VIH_ED
Conditions
IOL = 8mA
IOH = -8mA
CLOAD = 10pF
CLOAD = 10pF
MIN
VSS
0.68 *
VDDIO
0.68 *
VDDIO
VD0D.4IO -
InterfaceProtectDisable = 0
ULPI Synchronous Mode
At start-up or following
reset
55
55
TYP
1.19
1.56
67
67
MAX
0.8
VDDIO
VDD33
0.4
Units
V
V
V
V
V
nS
nS
±10 uA
4 pF
80 kΩ
77 kΩ
0.4 *
VDDIO
V
2012 - 2015 Microchip Technology Inc.
DS00001915B-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet USB3370.PDF ] | |
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