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PDF L9663 Data sheet ( Hoja de datos )

Número de pieza L9663
Descripción PSI5 Transceiver IC
Fabricantes STMicroelectronics 
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L9663
PSI5 Transceiver IC
Datasheet - production data
*$3*36
VFQFPN28
*$3*36
TQFP32
(Exposed pad down)
Features
2-channel PSI5 transceiver compatible with
rev. 1.3 and rev. 2.1
Manchester coded digital data transmission
High data transmission speed of 125 kbps
(optional 83.3 kbps and 189 kbps)
High EMC robustness and low emission
Bootstrap circuits for sync pulses
Current limitation and voltage clamp on
interface pins
Integrated charge pump stage for pre-
regulation with spread spectrum approach
Integrated FLL module for high accuracy timing
control
Reverse voltage protection structure
Short to ground tolerant with ±1.5 V ground
shift
32-bit SPI interface with address multiplexing
Operating voltage: VB = 4.8 V (5.2 V for sync
pulses with 3.5 V step) to 35 V
Ambient temperature range: -40°C to 140 °C
Package: VFQFPN28 or TQFP32EP
Description
The Peripheral Sensor Interface (PSI5) is an
interface for automotive sensor applications. PSI5
is an open standard based on existing sensor
interfaces for peripheral sensors and offers a
universal and flexible solution for multiple sensor
applications.
The PSI5 interface allows asynchronous or
synchronous operations and different bus modes.
The device is compatible with both v1.3 and v2.1
PSI5 revisions (limitations are specified inside this
document). It operates with a wide range of
sensor supply current and variable data word
length (8 to 28 bit).
The sensors are connected to the ECU using the
same line for power supply and data
transmission. The transceiver IC provides a pre-
regulated voltage to the sensors and reads in the
transmitted sensor data.
The PSI5 interface allows either point to point
connection or bussed mode.
Order code
L9663
L9663-TR
L9663-1
L9663-TR-1
Table 1. Device summary
Package
TQFP32 (Exposed pad)
VFQFPN28
Packing
Tray
Tape & Reel
Tray
Tape & Reel
January 2016
This is information on a product in full production.
DocID028693 Rev 1
1/104
www.st.com

1 page




L9663 pdf
L9663
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
VQFPN28 pins connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TQFP32 pins connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Supply line model for PSI5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-up sequence of transceiver IC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Internal power supply and reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Input structure of supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VAS application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block diagram Transceiver 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Internal oscillator vs external clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FLL clock error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Block diagram of incoming data buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PSI5 v1.3 frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PSI5 v2.0 frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Sensor buffer in synchronous mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Sensor buffer in asynchronous mode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Block diagram with interrupt pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ECU to sensor communication diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Short (in case 1 μs < tw < 5 μs) Sync Pulse trigger, compliant to PSI5 standard . . . . . . . . 38
Timing for PSIx under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Timing for PSIx reverse voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Timing for VAS under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Timing for sync pulse voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Operation on internal register (with upstream data buffer) . . . . . . . . . . . . . . . . . . . . . . . . . 84
Init data reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Sensor data reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Sync generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SPI communication timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
TQFP32 (7x7x1.0 mm exp. pad down) package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . 99
VFQFPN-28 (5x5x1.0 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
DocID028693 Rev 1
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5

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L9663 arduino
L9663
1.4
Overall description
TQFP32 pins description
Figure 3. TQFP32 pins connection diagram (top view)
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&/.,1
1&
6<1&
'287
1&
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6&/.
026,
1&
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Note:
*$3*36
The exposed pad is electrically shorted to the substrate and to pins GND1 and GND2.
These three nodes have to be kept shorted on the application.
Table 3. TQFP32 pin-out
Pin Name
Description
Pin type
1
SYNC1
Direct interface sync pulse trigger 1
I local
2
DOUT1
Direct interface 1/Interrupt 1
O local
3
CLKIN
External clock input
4
NC2
-
I local
--
5
SYNC2
Direct Interface sync pulse trigger 2
I local
6
DOUT2
Direct interface 2/Interrupt 2
7
NC(1)
-
O local
--
8
BH1
Bootstrap capacitor pin 1 or SYNC voltage
supply (from ECU), transceiver 1
I/O
local
9
BL1
Bootstrap capacitor pin 2, transceiver 1
I/O local
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