|
|
PDF ST2129 Data sheet ( Hoja de datos )
| Número de pieza | ST2129 | |
| Descripción | 2-bit dual supply level translator | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ST2129 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
ST2129
2-bit dual supply level translator
without direction control pin
Features
■ 42 MHz: 84 Mbps (max) data rate at
VL = 1.8 V, VCC = 3.3 V
■ Bidirectional level translation without direction
control pin
■ Wide voltage range (VCC ≥ VL):
– VL ranges from 1.65 to 3.6 V
– VCC ranges from 1.65 to 5.5 V
■ Power down mode feature - when VCC supply
is off, all I/Os are in high impedance
■ Totem-pole driving
■ 5.5 V tolerant enable pin
■ ESD performance on all pins : ±2 kv HBM
■ Small package and footprint:
QFN10 (1.8 x 1.4 mm)
Applications
■ Low voltage system level translation
■ Mobile phones and other mobile devices
QFN10
(1.8 x 1.4 mm)
Description
The ST2129 is a 2-bit dual supply level translator
which provides the level shifting capability to allow
data transfer in a multi-voltage system. Externally
applied voltages, VCC and VL, set the logic levels
on either side of the device. Its architecture allows
bidirectional level translation without a control pin.
The ST2129 accepts VL from 1.65 to 3.6 V and
VCC from 1.65 to 5.5 V, making it ideal for data
transfer between low-voltage ASICs/PLD and
higher voltage systems. This device has a tri-state
output mode which can be used to disable all
I/Os.
The ST2129 supports power-down mode when
VCC is grounded/floating or when the device is
disabled via the OE pin.
Table 1.
Device summary
Order Code
ST2129QTR
September 2009
Package
QFN10 (1.8 x 1.4 mm)
Doc ID 15967 Rev 1
Packaging
Tape & reel (3000 parts per reel)
1/20
www.st.com
20
1 page  
ST2129
3 Supplementary notes
Supplementary notes
3.1 Driver requirement
For proper operation, the driver from each side of the device must have the capability to
source and sink a minimum of 1mA current. The device architecture requires the driver to
source/sink a maximum current of (VCC/4) mA to/from the weak 4 kΩ output buffer.
3.2 Load driving capability
To support the architecture that allows level translation without direction pin, the one-shot
transistor is turned on only during state transition at the output side. After the one-shot
transistor is turned off, only the 4 kΩ resistor maintains the state. So, resistive load or pull-up
resistor less than 50 kΩ is not recommended for a proper operation.
3.3 Power off feature
In some applications, where it might be required to turn off one of the power supplies
powering up the level translator, the device is automatically disabled when VCC supply is
turned off, even if the OE pin is set to HIGH (enabled). In this mode, all I/Os are in high
impedance state.
3.4 Truth table
Table 3.
Truth table
Enable
OE
H(1)
H(1)
L
Bidirectional Input/Output
I/OVCC
H(2)
L
Z(3)
I/OVL
H(1)
L
Z(3)
(1) High level VL power supply referred.
(2) High level VCC power supply referred.
(3) Z = High impedance.
Doc ID 15967 Rev 1
5/20
5 Page 
ST2129
AC characteristics
Table 9.
Symbol
AC characteristics - test conditions: VL = 2.3 – 2.7 V
Parameter
VCC = 2.3 – 2.7 V VCC = 3.0 – 3.6 V
Min Max Min Max
VCC = 4.5 – 5.5 V
Min Max
Unit
tRVCC Rise time I/OVCC
– 3.3 – 2.2 – 1.6 ns
tFVCC Fall time I/OVCC
– 1.7 – 1.6 – 1.4 ns
tRVL Rise time I/OVL
– 2.2 – 2.0 – 1.9 ns
tFVL Fall time I/OVL
– 1.3 – 1.2 – 1.2 ns
Propagation delay
time
tI/OVL-VCC I/OVL-LH to I/OVCC-
LH
I/OVL-HL to I/OVCC-
HL
tPLH
tPHL
– 4.6 – 4.3 – 3.9 ns
– 3.6 – 3.3 – 2.9 ns
Propagation delay
time
tI/OVCC-VL I/OVCC-LH to I/OVL-
LH
I/OVCC-HL to I/OVL-
HL
tPLH
tPHL
– 3.9 – 3.5 – 3.5 ns
– 3.6 – 3.0 – 2.5 ns
tPZL tPZH Output enable time
tPLZ tPHZ Output disable time
DR Data rate(1)
– 20 – 20 – 20
ns
– 130 – 130 – 130
84 – 85 – 88 – Mbps
1. Data rate is guaranteed based on the condition that output I/O signal rise/fall time is less than 15% of period of input I/O
signal; input I/O signal is at 50% duty-cycle and output I/O signal duty-cycle deviation is less than 50% ± 10%.
Table 10.
Symbol
AC characteristics - test conditions: VL = 3.0 – 3.6 V
Parameter
VCC = 3.0 – 3.6 V
Min Max
tRVCC Rise time I/OVCC
tFVCC Fall time I/OVCC
tRVL Rise time I/OVL
tFVL Fall time I/OVL
tI/OVL-VCC
Propagation delay time
I/OVL-LH to I/OVCC-LH
I/OVL-HL to I/OVCC-HL
tPLH
tPHL
tI/OVCC-VL
Propagation delay time
I/OVCC-LH to I/OVL-LH
I/OVCC-HL to I/OVL-HL
tPLH
tPHL
– 1.8
– 1.3
– 1.6
– 1.1
– 4.1
– 2.6
– 4.0
– 2.6
VCC = 4.5 – 5.5 V
Min Max
– 1.7
– 1.2
– 1.5
– 1.1
– 4.1
– 2.3
– 4.0
– 2.4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Doc ID 15967 Rev 1
11/20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ST2129.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ST2123 | CMOS Positive Voltage Regulator |  SeCoS |
| ST2129 | 2-bit dual supply level translator | STMicroelectronics |
| ST2129B | 2-bit dual supply level translator | STMicroelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |