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PDF M35B32 Data sheet ( Hoja de datos )
| Número de pieza | M35B32 | |
| Descripción | fast program EEPROM memory | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de M35B32 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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M35B32
32 Kbit, 256-byte page, fast program EEPROM memory
accessed by SPI bus interface
Datasheet - target specification
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
UFDFPN8 (MC)
2 x 3 mm
Features
• SPI bus compatible serial interface
• 32 Kbit of EEPROM divided into two sectors:
– Data sector
– Event sector
• Large page size: 256 bytes
• Fast programming:
– Event sector: 256 bytes programmed in
less than 1 ms
– Data sector: 256 bytes written in less than
5 ms
• Low energy EEPROM in either Read, Write,
Program or Erase modes
• 2.5 V to 5.5 V single supply voltage
• Operating temperature range:
• – 40°C to +85°C
• – 40°C to +125°C
• Operating frequency, fC = 20 MHz
• Electronic signature: 20 10 0Ch
• Data cycling:
– Data sector: more than 1 Million write
cycles
– Event sector: more than 10 000 write
cycles
• Data retention:
– Data sector: more than 40 years’ data
retention
– Event sector: 1 year
Packages
• SO8 ECOPACK®2
• TSSOP8 ECOPACK®2
• UFDFPN8 ECOPACK®2
May 2015
DocID18391 Rev 4
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
1/44
www.st.com
1 page  
M35B32
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 18
Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 20
Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 22
Page Write (PW) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Page Erase (PE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Write Protect setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 37
SO8N – 8-lead plastic small outline, 150 mils body width,
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.5 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch
dual flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DocID18391 Rev 4
5/44
5
5 Page 
M35B32
SPI modes
Figure 4. Bus master and memory devices on the SPI bus
2
30) )NTERFACE WITH
#0/, #0(!
OR
3$/
3$)
3#+
30) "US -ASTER
633
6##
#1$
6##
633
#1$
6##
633
#1$
6##
633
#3 #3 #3
2 30) -EMORY 2
$EVICE
30) -EMORY 2
$EVICE
30) -EMORY
$EVICE
3
7 2%3%4
3
7 2%3%4
3
7 2%3%4
2EFER TO .OTE
2EFER TO .OTE
2EFER TO .OTE
Note:
1 The /W and /RESET inputs are CMOS inputs and have also to be driven high or low if/when the SPI
bus master leaves the lines in high impedance. This has to be done with the help of pull up or pull
down resistors (depending on the application requirements).
Figure 4 shows an example of three devices connected to an MCU, on an SPI bus. Only
one device is selected at a time, so only one device drives the Serial Data Output (Q) line at
a time, the other devices are high impedance.
A pull-up resistor connected on each /S input (represented in Figure 4) ensures that each
slave device on the SPI bus is not selected if the bus master leaves the /S line in the high
impedance state.
In applications where the bus master might enter a state where all inputs/outputs SPI lines
are in high impedance at the same time (for example, if the Bus Master is reset during the
transmission of an instruction), the clock line (C) must be connected to an external pull-
down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high). This ensures that S and C do not become high at the same
time, and so, that the tSHCH requirement is met.
DocID18391 Rev 4
11/44
43
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M35B32.PDF ] | |
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