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PDF 8T49N242 Data sheet ( Hoja de datos )
| Número de pieza | 8T49N242 | |
| Descripción | NG Universal Frequency Translator | |
| Fabricantes | Integrated Device Technology | |
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FemtoClock® NG Universal Frequency
Translator
8T49N242
Datasheet
General Description
The 8T49N242 has one fractional-feedback PLL that can be used as
a jitter attenuator and frequency translator. It is equipped with four
integer output dividers, allowing the generation of up to four different
output frequencies, ranging from 8kHz to 1GHz. These frequencies
are completely independent of the input reference frequencies and
the crystal reference frequency. The device places virtually no
constraints on input to output frequency conversion, supporting all
FEC rates, including the new revision of ITU-T Recommendation
G.709 (2009), most with 0ppm conversion error. The outputs may
select among LVPECL, LVDS, HCSL or LVCMOS output levels.
This makes it ideal to be used in any frequency synthesis application,
including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and
SONET/SDH, including ITU-T G.709 (2009) FEC rates.
The 8T49N242 accepts up to two differential or single-ended input
clocks and a fundamental-mode crystal input. The internal PLL can
lock to either of the input reference clocks or just to the crystal to
behave as a frequency synthesizer. The PLL can use the second
input for redundant backup of the primary input reference, but in this
case, both input clock references must be related in frequency.
The device supports hitless reference switching between input
clocks. The device monitors both input clocks for Loss of Signal
(LOS), and generates an alarm when an input clock failure is
detected. Automatic and manual hitless reference switching options
are supported. LOS behavior can be set to support gapped or
un-gapped clocks.
The 8T49N242 supports holdover. The holdover has an initial
accuracy of ±50ppB from the point where the loss of all applicable
input reference(s) has been detected. It maintains a historical
average operating point for the PLL that may be returned to in
holdover at a limited phase slope.
The PLL has a register-selectable loop bandwidth from 0.2Hz to
6.4kHz.
The device supports Output Enable & Clock Select inputs and Lock,
Holdover & LOS status outputs.
The device is programmable through an I2C interface. It also
supports I2C master capability to allow the register configuration to
be read from an external EEPROM.
Programming with IDT’s Timing Commander software is
recommended for optimal device performance. Factory
pre-programmed devices are also available.
Applications
• OTN or SONET / SDH equipment
• Gigabit and Terabit IP switches / routers including Synchronous
Ethernet
• Video broadcast
Features
• Supports SDH/SONET and Synchronous Ethernet clocks including
all FEC rate conversions
• 0.35ps RMS Typical Jitter (including spurs): 12kHz to 20MHz
• Operating Modes: Synthesizer, Jitter Attenuator
• Operates from a 10MHz to 50MHz fundamental-mode crystal or a
10MHz to 125MHz external oscillator
• Initial holdover accuracy of +50ppb.
• Accepts up to 2 LVPECL, LVDS, LVHSTL or LVCMOS input clocks
• Accepts frequencies ranging from 8kHz to 875MHz
• Auto and manual clock selection with hitless switching
• Clock input monitoring including support for gapped clocks
• Phase-slope limiting and fully hitless switching options to control
output clock phase transients
• Generates four LVPECL / LVDS / HCSL or eight LVCMOS output
clocks
• Output frequencies ranging from 8kHz up to 1.0GHz
(differential)
• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
• Integer divider ranging from ÷4 to ÷786,420 for each output
• Programmable loop bandwidth settings from 0.2Hz to 6.4kHz
• Optional fast-lock function
• Four General Purpose I/O pins with optional support for status &
control:
• Two Output Enable control inputs provide control over the four
clocks
• Manual clock selection control input
• Lock, Holdover and Loss-of-Signal alarm outputs
• Open-drain Interrupt pin
• Register programmable through I2C or via external I2C EEPROM
• Full 2.5V or 3.3V supply modes, 1.8V support for LVCMOS outputs,
GPIO and control pins
• -40°C to 85°C ambient operating temperature
• Package: 40QFN, lead-free (RoHS 6)
©2016 Integrated Device Technology, Inc.
1
REVISION 6, November 1, 2016
1 page  
8T49N242 Datasheet
Number
32
33
34
35
Name
VCCA
OSCI
OSCO
nWP
Type1
Power
I
O
I Pullup
Description
Analog function supply for core analog functions. 2.5V or 3.3V supported.
Crystal Input. Accepts a 10MHz – 50MHz reference from a clock oscillator or a
12pF fundamental mode, parallel-resonant crystal. For proper device
functionality, a crystal or external oscillator must be connected to this pin.
Crystal Output. This pin must be connected to a crystal. If an oscillator is
connected to OSCI, then this pin must be left unconnected.
Write Protect input. LVTTL / LVCMOS interface levels.
0 = Write operations on the serial port will complete normally, but will have no
effect except on interrupt registers.
36
VCCCS
Power
Output supply for Control & Status pins:
GPIO[3:0], SDATA, SCLK, S_A1, S_A0, nINT, nWP, nRST
1.8V, 2.5V or 3.3V supported
37
CAP
Analog
PLL External Capacitance. A 0.1µF capacitance value across CAP and
CAP_REF pins is recommended.
38
CAP_REF
Analog
PLL External Capacitance. A 0.1µF capacitance value across CAP and
CAP_REF pins is recommended.
39
40
ePAD
VCCA
S_A0
Exposed Pad
Power
I
Power
Pulldown
Analog function supply for analog functions associated with PLL. 2.5V or 3.3V
supported.
I2C Address Bit A0.
Negative supply voltage. All VEE pins and ePAD must be connected before any
positive supply voltage is applied.
NOTE 1: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics, VCC = VCCOX = 3.3V±5% or 2.5V±5%1
Symbol
CIN
RPULLUP
Parameter
Input Capacitance2
Input Pullup
Resistor
GPIO[3:0],
nRST, nWP,
SDATA, SCLK
Test Conditions
Input Pulldown
RPULLDOWN Resistor
S_A0, S_A1
LVCMOS
VCCOX = 3.465V
Power Dissipation LVCMOS
VCCOX = 2.625V
CPD
Capacitance
LVCMOS
VCCOX = 1.89V
(per output pair)
LVDS, HCSL or
LVPECL
VCCOX = 3.465V or 2.625V
ROUT
Output
Impedance
GPIO[3:0]
LVCMOS
Q[3:0], nQ[3:0]
VCCCS = 3.3V
VCCCS = 2.5V
VCCCS = 1.8V
VCCOX = 3.3V
VCCOX = 2.5V
VCCOX = 1.8V
NOTE 1: VCCOX denotes: VCCO0, VCCO1, VCCO2 or VCCO3.
NOTE 2: This specification does not apply to the OSCI or OSCO pins.
Minimum
Typical
3.5
Maximum Units
pF
51 k
51 k
11.5 pF
10.5 pF
11 pF
2.5 pF
26
30
42
18
22
30
©2016 Integrated Device Technology, Inc.
5
Revision 6, November 1, 2016
5 Page 
8T49N242 Datasheet
I2C Mode Operation
The I2C interface is designed to fully support v1.2 of the I2C
Specification for Normal and Fast mode operation. The device acts
as a slave device on the I2C bus at 100kHz or 400kHz using the
address defined in the Serial Interface Control register (0006h), as
modified by the S_A0 & S_A1 input pin settings. The interface
accepts byte-oriented block write and block read operations. Two
address bytes specify the register address of the byte position of the
first register to write or read. Data bytes (registers) are accessed in
sequential order from the lowest to the highest byte (most significant
Current Read
bit first). Read and write block transfers can be stopped after any
complete byte transfer. During a write operation, data will not be
moved into the registers until the STOP bit is received, at which point,
all data received in the block write will be written simultaneously.
For full electrical I2C compliance, it is recommended to use external
pull-up resistors for SDATA and SCLK. The internal pull-up resistors
have a size of 51k typical.
S Dev Addr + R A Data 0 A Data 1 A
A Data n Ā P
Sequential Read
S
Dev Addr + W
A Offset Addr MSB A Offset Addr LSB A Sr
Dev Addr + R
A
Data 0
A
Data 1
A
A Data n Ā P
Sequential Write
S Dev Addr + W A Offset Addr MSB A Offset Addr LSB A Data 0 A Data 1 A
A Data n A P
from master to slave
from slave to master
S = start
Sr = repeated start
A = acknowledge
A = non‐acknowledge
P = stop
Figure 5. I2C Slave Read and Write Cycle Sequencing
I2C Master Mode
When operating in I2C mode, the 8T49N242 has the capability to
become a bus master on the I2C bus for the purposes of reading its
configuration from an external I2C EEPROM. Only a block read cycle
will be supported.
As an I2C bus master, the 8T49N242 will support the following
functions:
• 7-bit addressing mode
• Base address register for EEPROM
• Validation of the read block via CCITT-8 CRC check against value
stored in last byte (84h) of EEPROM
• Support for 100kHz and 400kHz operation with speed negotiation.
If bit d0 is set at Byte address 05h in the EEPROM, this will shift
from 100kHz operation to 400kHz operation.
• Support for 1- or 2-byte addressing mode
• Master arbitration with programmable number of retries
• Fixed-period cycle response timer to prevent permanently hanging
the I2C bus.
• Read will abort with an alarm (BOOTFAIL) if any of the following
conditions occur: Slave NACK, Arbitration Fail, Collision during
Address Phase, CRC failure, Slave Response time-out
The 8T49N242 will not support the following functions:
• I2C General Call
• Slave clock stretching
• I2C Start Byte protocol
• EEPROM Chaining
• CBUS compatibility
• Responding to its own slave address when acting as a master
• Writing to external I2C devices including the external EEPROM
used for booting
©2016 Integrated Device Technology, Inc.
11
Revision 6, November 1, 2016
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 8T49N242.PDF ] | |
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