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PDF 8T49N241 Data sheet ( Hoja de datos )

Número de pieza 8T49N241
Descripción NG Universal Frequency Translator
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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No Preview Available ! 8T49N241 Hoja de datos, Descripción, Manual

FemtoClock® NG Universal Frequency
Translator
8T49N241
Datasheet
General Description
The 8T49N241 has one fractional-feedback PLL that can be used as
a jitter attenuator and frequency translator. It is equipped with one
integer and three fractional output dividers, allowing the generation
of up to four different output frequencies, ranging from 8kHz to 1GHz.
These frequencies are completely independent of each other, the
input reference frequencies and the crystal reference frequency. The
device places virtually no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error. The outputs may select among LVPECL, LVDS, HCSL or
LVCMOS output levels.
This makes it ideal to be used in any frequency synthesis application,
including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and
SONET/SDH, including ITU-T G.709 (2009) FEC rates.
The 8T49N241 accepts up to two differential or single-ended input
clocks and a fundamental-mode crystal input. The internal PLL can
lock to either of the input reference clocks or just to the crystal to
behave as a frequency synthesizer. The PLL can use the second
input for redundant backup of the primary input reference, but in this
case, both input clock references must be related in frequency.
The device supports hitless reference switching between input
clocks. The device monitors both input clocks for Loss of Signal
(LOS), and generates an alarm when an input clock failure is
detected. Automatic and manual hitless reference switching options
are supported. LOS behavior can be set to support gapped or
un-gapped clocks.
The 8T49N241 supports holdover. The holdover has an initial
accuracy of ±50ppB from the point where the loss of all applicable
input reference(s) has been detected. It maintains a historical
average operating point for the PLL that may be returned to in
holdover at a limited phase slope.
The PLL has a register-selectable loop bandwidth from 0.2Hz to
6.4kHz.
The device supports Output Enable & Clock Select inputs and Lock,
Holdover & LOS status outputs.
The device is programmable through an I2C interface. It also
supports I2C master capability to allow the register configuration to
be read from an external EEPROM.
Programming with IDT’s Timing Commander software is
recommended for optimal device performance. Factory
pre-programmed devices are also available.
Applications
• OTN or SONET / SDH equipment
• Gigabit and Terabit IP switches / routers including Synchronous
Ethernet
• Video broadcast
Features
• Supports SDH/SONET and Synchronous Ethernet clocks including
all FEC rate conversions
• 0.35ps RMS Typical Jitter (including spurs): 12kHz to 20MHz
• Operating Modes: Synthesizer, Jitter Attenuator
• Operates from a 10MHz to 50MHz fundamental-mode crystal or a
10MHz to 125MHz external oscillator
• Initial holdover accuracy of +50ppb.
• Accepts up to 2 LVPECL, LVDS, LVHSTL or LVCMOS input clocks
• Accepts frequencies ranging from 8kHz to 875MHz
• Auto and manual clock selection with hitless switching
• Clock input monitoring including support for gapped clocks
• Phase-slope limiting and fully hitless switching options to control
output clock phase transients
• Generates four LVPECL / LVDS / HCSL or eight LVCMOS output
clocks
• Output frequencies ranging from 8kHz up to 1.0GHz
(differential)
• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
• One integer divider ranging from ÷4 to ÷786,420
• Three fractional output dividers (see Section, “Output Dividers”)
• Programmable loop bandwidth settings from 0.2Hz to 6.4kHz
• Optional fast-lock function
• Four General Purpose I/O pins with optional support for status &
control:
• Two Output Enable control inputs provide control over the four
clocks
• Manual clock selection control input
• Lock, Holdover and Loss-of-Signal alarm outputs
• Open-drain Interrupt pin
• Register programmable through I2C or via external I2C EEPROM
• Full 2.5V or 3.3V supply modes, 1.8V support for LVCMOS outputs,
GPIO and control pins
• -40°C to 85°C ambient operating temperature
• Package: 40QFN, lead-free (RoHS 6)
©2016 Integrated Device Technology, Inc.
1
REVISION 6, October 31, 2016

1 page




8T49N241 pdf
8T49N241 Datasheet
Number
30
31
Name
VCCA
nRST
Type1
Power
I Pullup
Description
Analog function supply for analog functions associated with PLL. 2.5V or 3.3V
supported.
Master Reset input. LVTTL / LVCMOS interface levels:
0 = All registers and state machines are reset to their default values
1 = Device runs normally
32
VCCA
Power
33 OSCI I
34
OSCO
O
Analog function supply for core analog functions. 2.5V or 3.3V supported.
Crystal Input. Accepts a 10MHz – 50MHz reference from a clock oscillator or a
12pF fundamental mode, parallel-resonant crystal. For proper device
functionality, a crystal or external oscillator must be connected to this pin.
Crystal Output. This pin must be connected to a crystal. If an oscillator is
connected to OSCI, then this pin must be left unconnected.
Write Protect input. LVTTL / LVCMOS interface levels.
35 nWP I Pullup 0 = Write operations on the serial port will complete normally, but will have no
effect except on interrupt registers.
36
VCCCS
Power
Output supply for Control & Status pins:
GPIO[3:0], SDATA, SCLK, S_A1, S_A0, nINT, nWP, nRST
1.8V, 2.5V or 3.3V supported
37
CAP
Analog
PLL External Capacitance. A 0.1µF capacitance value across CAP and
CAP_REF pins is recommended.
38
CAP_REF
Analog
PLL External Capacitance. A 0.1µF capacitance value across CAP and
CAP_REF pins is recommended.
39
VCCA
Power
Analog function supply for analog functions associated with PLL. 2.5V or 3.3V
supported.
40 S_A0 I Pulldown I2C Address Bit A0.
ePAD
Exposed Pad Power
Negative supply voltage. All VEE pins and ePAD must be connected before any
positive supply voltage is applied.
NOTE 1: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2016 Integrated Device Technology, Inc.
5
Revision 6, October 31, 2016

5 Page





8T49N241 arduino
8T49N241 Datasheet
General-Purpose I/Os & Interrupts
The 8T49N241 provides four General Purpose Input / Output (GPIO)
pins for miscellaneous status & control functions. Each GPIO may be
configured as either an input or an output. Each GPIO may be directly
controlled from register bits or be used as a predefined function as
shown in Table 4. Note that the default state prior to configuration
being loaded from internal OTP will be to set each GPIO to input
direction to function as an Output Enable.
Table 4. GPIO Configuration1
Configured as Input
Configured as Output
GPIO Pin
Fixed
Function
(default)
General
Purpose
Fixed
Function
General
Purpose
3
-
GPI[3]
LOL GPO[3]
2
CSEL
GPI[2]
LOS[0]
GPO[2]
1
OSEL[1]
GPI[1]
LOS[1]
GPO[1]
0
OSEL[0]
GPI[0]
HOLD
GPO[0]
NOTE 1:
GPI[x]: General Purpose Input. Logic state on GPIO[x] pin is directly
reflected in GPI[x] register.
LOL: Loss-of-Lock Status Flag for Digital PLL. Logic-high indicates
digital PLL not locked.
GPO[x]: General Purpose Output. Logic state is determined by value
written in register GPO[x].
OSEL[n]: Output Enable Control Signals for Outputs Qx, nQx. Refer
to Output Enable Operation section.
LOS[x]: Loss-of-Signal Status Flag for Input Reference x. Logic-high
indicates input reference failure.
CSEL: Manual Clock Select Input for PLL. Logic-high selects differ-
ential clock input 1 (CLK1).
HOLD: Holdover Status Flag for Digital PLL. Logic-high indicates dig-
ital PLL in holdover status.
Refer to Section, “Register Descriptions” for additional details.
If used in the Fixed Function mode of operation, the GPIO bits will
reflect the real-time status of their respective status bits as shown in
Table 4.
The LOL alarm will support two modes of operation:
• De-asserts once PLL is locked, or
• De-asserts after PLL is locked and all internal synchronization
operations that may destabilize output clocks are completed.
Interrupt Functionality
Interrupt functionality includes an interrupt status flag for each of PLL
Loss-of-Lock status (LOL), PLL in holdover status (HOLD) and
Loss-of-Signal status for each input (LOS[1:0]). Those Status Flags
are set whenever there is an alarm on their respective functions. The
Status Flag will remain set until the alarm has been cleared and a ‘1’
has been written to the Status Flag’s register location or if a reset
occurs. Each Status Flag will also have an Interrupt Enable bit that
will determine if that Status Flag is allowed to cause the Device
Interrupt Status to be affected (enabled) or not (disabled). All
Interrupt Enable bits will be in the disabled state after reset. The
Device Interrupt Status Flag and nINT output pin are asserted if any
of the enabled interrupt Status Flags are set.
Output Enable Operation
When GPIO[1:0] are used as Output Enable control signals, the
function of the pins is to select one of four register-based maps that
indicate which outputs should be enabled or disabled.
00
Q0 Q1 Q2 Q3
EN EN EN EN
0 1 DIS EN EN DIS
1 0 EN DIS EN DIS
4
1 1 DIS DIS DIS DIS
Figure 4. Output Enable Map Operation
Device Hardware Configuration
The 8T49N241 supports an internal One-Time Programmable (OTP)
memory that can be pre-programmed at the factory with one
complete device configuration. Some or all of this pre-programmed
configuration will be loaded into the device’s registers on power-up or
reset.
These default register settings can be over-written using the serial
programming interface once reset is complete. Any configuration
written via the serial programming interface needs to be re-written
after any power cycle or reset. Please contact IDT if a specific
factory-programmed configuration is desired.
©2016 Integrated Device Technology, Inc.
11
Revision 6, October 31, 2016

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