|
|
PDF 8V44N4614 Data sheet ( Hoja de datos )
| Número de pieza | 8V44N4614 | |
| Descripción | NG Jitter Attenuator and Clock Synthesizer | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 8V44N4614 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
FemtoClock® NG Jitter Attenuator and
Clock Synthesizer
8V44N4614
DATA SHEET
General Description
The 8V44N4614 is a FemtoClock® NG Clock Generator. The device
has been designed for frequency generation in high-performance
systems such wireless base-band boards, for instance to drive the
reference clock inputs of processors, PHY, switch and SerDes
devices. The device is very flexible in frequency programming. It
allows to generate the clock frequencies of 156.25MHz, 125MHz,
100MHz and 25MHz individually at three output banks. One output
bank supports configurable LVDS, LVPECL, the other two output
banks support LVCMOS output levels. All outputs are synchronized
on the incident rising edge, regardless of the selected output
frequency. Selective single-ended LVCMOS outputs can be
configured to invert the output phase, effectively forming differential
LVCMOS output pairs for noise reduction. The PLL reference signal
is either a 25MHz, 50MHz, 100MHz or 200MHz differential or
single-ended clock.
The device is optimized to deliver excellent period and cycle-to-cycle
jitter performance, combined with good phase noise performance,
and high power supply noise rejection.
The device is configured through an SPI serial interface. Outputs can
be configured to any of the available output frequencies. Two
hardware pins are available for selecting pre-set output enable/
disable configurations. In each of these pre-set configurations, each
output can be enabled/disabled individually. A separate test mode is
available for an increase or decrease of the output frequencies in
19.53125ppm steps independent on the input frequency. The device
is packaged in a lead-free (RoHS 6) 48-lead VFQFN package. The
extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
Features
• Clock generator for wireless base-band systems
• Drives reference clock inputs of processors, PHY, switch and
SerDes devices
• FemtoClock® NG technology
• Three low-skew, differential LVDS, LVPECL configurable clock
outputs
• Ten low-skew, LVCMOS/LVTTL clock outputs
• Input: 200MHz, 100MHz, 50MHz, 25MHz single-ended
(LVCMOS) or differential reference clock (LVDS, LVPECL)
• Output clocks support 156.25MHz, 125MHz, 100MHz and 25MHz
• Individual output disable (high-impedance)
• Two sets of output enable configurations
• PLL lock detect output
• Test mode with frequency margining with 19.53125ppm steps
(range ±507.8125ppm)
• LVCMOS (1.8V, JESD8-7A) compatible SPI programming
interface
• Cycle-to-cycle jitter: 10ps (typical)
• RMS period jitter: 1.6ps (typical)
• Phase noise (12kHz - 20MHz): 0.40ps (typical)
• 3.3V core and output supply
• -40°C to +85°C ambient operating temperature
• Lead-free (RoHS 6) 48-lead VFQFN packaging
REVISION 1 02/25/15
1 ©2015 INTEGRATED DEVICE TECHNOLOGY, INC.
1 page  
8V44N4614 DATA SHEET
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLUP
RPULLDOWN
ROUT
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output
QA[3:4], QB[0:3],
Impedance QC[0:3]
Test Conditions
VDDOA, VDDOB, VDDOC = 3.3V
Minimum
Typical
4
51
51
25
Maximum
Units
pF
k
k
REVISION 1 02/25/15
5 FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
5 Page 
8V44N4614 DATA SHEET
Divider Control Register
Table 4B. Divider Control Register Bit Allocations
Register Bit
Register
D7 D6 D5 D4 D3 D2 D1 D0
1 P1 P0 NC1 NC0 NB1 NB0 NA1 NA0
Table 4C. Divider Control Register Function Descriptions
Bits
Name
Factory Default
Function
These bits control the selection of the divider N for the output clock:
Nm[1:0]
Output Divider
Setting
NA = 01
NB = 11
NC = 10
00
01
10
÷16
÷20
÷25
11 ÷100
These bits control the selection of the input pre-divider P:
P[1:0]
PLL Pre-Divider
Setting
P = 11
00
01
10
÷1
÷2
÷4
11 ÷8
m = Output bank A, B, C
LVCMOS Output Control Register
Table 4D. LVCMOS Output Control Register Bit Allocations
Register Bit
Register
D7 D6 D5 D4 D3
2
INVC1
INVC0
INVB3
INVB2
INVB1
3
INVC3
INVC2
Reserved ENA_QA4 ENA_QA3
D2
INVB0
ENA_QA2
D1
INVA4
ENA_QA1
D0
INVA3
ENA_QA0
Table 4E. LVCMOS Output Control Register Function Descriptions
Bits Name
Factory Default
Function
INVn
Output Phase Inversion
Reg 2: 1010 1010
Reg 3: 1000 1101
0 = Qn output phase is normal (0°)
1 = Qn output phase is inverted (180°)
REVISION 1 02/25/15
11 FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 8V44N4614.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 8V44N4614 | NG Jitter Attenuator and Clock Synthesizer | Integrated Device Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |