PDF X9111 Data sheet ( Hoja de datos )

Número de pieza	X9111
Descripción	Single Digitally Controlled Potentiometer
Fabricantes	Intersil
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No Preview Available ! ® Data Sheet X9111 Single Supply/Low Power/1024-Tap/SPI Bus September 15, 2006 FN8159.4 Single Digitally-Controlled (XDCP™) Potentiometer The X9111 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 1023 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Functional Diagram VCC Features • 1024 Resistor Taps – 10-Bit Resolution • SPI Serial Interface for Write, Read, And Transfer Operations Of The Potentiometer • Wiper Resistance, 40Ω Typical @ 5V • Four Non-Volatile Data Registers • Non-Volatile Storage of Multiple Wiper Positions • Power On Recall. Loads Saved Wiper Position on Power-Up. • Standby Current <3µA Max • VCC: 2.7V to 5.5V Operation • 100kΩ End to End Resistance • 100 yr. Data Retention • Endurance: 100,000 Data Changes Per Bit Per Register • 14 Ld TSSOP • Low Power CMOS • Single Supply Version of the X9110 • Pb-Free Plus Anneal Available (RoHS Compliant) Pinout SO A0 NC CS SCK SI VSS TSSOP 1 14 2 13 3 12 4 X9111 11 5 10 69 78 VCC RL RH RW HOLD A1 WP RH SPI Bus Interface Address Data Status Bus Interface & Control Write Read Transfer Control Power On Recall Wiper Counter Register (WCR) Data Registers (DR0-DR3) Wiper 100kΩ 1024-taps POT VSS NC RW RL 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 \| Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved XDCP is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners. 1 page X9111 bits is required for the X9111 to successfully continue the command sequence. Only the device whose slave address matches the incoming device address sent by the master executes the instruction. The A1–A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. The R/W bit is used to set the device to either read or write mode. Instruction Byte and Register Selection The next byte sent to the X9111 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (I[2:0]). The RB and RA bits point to one of the four registers. The format is shown in Table 5. TABLE 1. WIPER LATCH, WL (10-BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V) WCR9 WCR8 WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0 VVVVVVVVVV (MSB) (LSB) TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE, NV) BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 NV NV NV NV NV NV NV NV NV NV MSB LSB TABLE 3. STATUS REGISTER, SR (1-BIT) WIP (LSB) ID3 0 (MSB) TABLE 3. IDENTIFICATION BYTE FORMAT Device Type Identifier Internal Slave Address ID2 ID1 ID0 0 A1 A0 101 Read or Write Bit R/W (LSB) I2 (MSB) Instruction Opcode I1 TABLE 4. INSTRUCTION BYTE FORMAT Register Selection I0 0 RB RA RB RA REGISTER 00 01 10 11 DR0 DR1 DR2 DR3 0 0 (LSB) 5 FN8159.4 September 15, 2006 5 Page Equivalent A.C. Load Circuit 5V SO pin 2714Ω 1462Ω 100pF X9111 3V SO pin 1382Ω 1217Ω 100pF AC Timing SYMBOL PARAMETER fSCK tCYC tWH tWL tLEAD tLAG tSU tH tRI tFI tDIS tV tHO tRO tFO tHOLD tHSU tHH tHZ tLZ TI SSI/SPI clock frequency SSI/SPI clock cycle time SSI/SPI clock high time SSI/SPI clock low time Lead time Lag time SI, SCK, HOLD and CS input setup time SI, SCK, HOLD and CS input hold time SI, SCK, HOLD and CS input rise time SI, SCK, HOLD and CS input fall time SO output disable time SO output valid time SO output hold time SO output rise time SO output fall time HOLD time HOLD setup time HOLD hold time HOLD low to output in high Z HOLD high to output in low Z Noise suppression time constant at SI, SCK, HOLD and CS inputs tCS tWPASU tWPAH CS deselect time WP, A0, A1 setup time WP, A0, A1 hold time SPICE Macromodel RTOTAL RH RL CL CW CL 10pF 10pF 25pF RW MIN MAX UNITS 2.0 MHz 400 ns 150 ns 150 ns 150 ns 150 ns 50 ns 50 ns 50 ns 50 ns 0 500 ns 100 ns 0 ns 50 ns 50 ns 400 ns 50 ns 50 ns 100 ns 100 ns 20 ns 100 ns 0 ns 0 ns 11 FN8159.4 September 15, 2006 11 Page

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