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PDF X9110 Data sheet ( Hoja de datos )
| Número de pieza | X9110 | |
| Descripción | Single Digitally Controlled Potentiometer | |
| Fabricantes | Intersil | |
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Data Sheet
X9110
Dual Supply/Low Power/1024-Tap/SPI Bus
February 13, 2008
FN8158.3
Single Digitally-Controlled (XDCP™)
Potentiometer
The X9110 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
circuit.
The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the SPI bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Functional Diagram
VCC
Features
• 1024 Resistor Taps – 10-Bit Resolution
• SPI Serial Interface for write, read, and transfer operations
of the potentiometer
• Wiper Resistance, 40Ω Typical @ 5V
• Four Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on Power-up
• Standby Current < 3µA Max
• System VCC: 2.7V to 5.5V Operation
• Analog V+/V-: -5V to +5V
• 100kΩ End to End Resistance
• 100 yr. Data Retention
• Endurance: 100, 000 Data Changes Per Bit Per Register
• 14 Ld TSSOP
• Dual Supply Version of the X9111
• Low Power CMOS
• Pb-Free Available (RoHS Compliant)
Pinout
V+
S0
A0
SCK
WP
SI
VSS
X9110
14 LD TSSOP
TOP VIEW
1 14
2 13
3 12
4 11
5 10
69
78
VCC
RL
RH
RW
HOLD
CS
V-
RH V+
SPI
BUS
INTERFACE
ADDRESS
DATA
STATUS
BUS
INTERFACE &
CONTROL
WRITE
READ
TRANSFER
CONTROL
POWER-ON RECALL
WIPER COUNTER
REGISTER (WCR)
DATA REGISTERS
(DR0-DR3)
WIPER
100kΩ
1024-TAPS
POT
VSS NC NC
RW RL
V-
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas INC. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
X9110
may be written indirectly by transferring the contents of one
of four associated Data Registers via the XFR Data Register;
(3) it is loaded with the contents of its data register zero
(DR0) upon power-up.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9110 is powered-down. Although
the register is automatically loaded with the value in DR0 upon
power-up, this may be different from the value present at
power-down. Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR.
DATA REGISTERS (DR)
The potentiometer has four 10-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the Wiper Counter Register. All operations
changing data in one of the Data Registers is a nonvolatile
operation and will take a maximum of 10ms.
DR[9:0] is used to store one of the 1024 wiper position
(0~1023) (see Table 2).
STATUS REGISTER (SR)
This 1-bit status register is used to store the system status
(see Table 3).
WIP: Write In Progress status bit, read only.
• When WIP = 1, indicates that high-voltage write cycle is in
progress.
• When WIP=0, indicates that no high-voltage write cycle is
in progress.
TABLE 1. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9–WCR0: Used To Store The Current Wiper Position (Volatile, V)
WCR9
WCR8
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
VVVVVVVVVV
(MSB)
(LSB)
BIT 9
NV
MSB
TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: Used to store wiper positions or data (Non-Volatile, NV)
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
NV NV NV NV NV NV NV NV
TABLE 3. STATUS REGISTER, SR (1-BIT)
WIP
(LSB)
BIT 0
NV
LSB
5 FN8158.3
February 13, 2008
5 Page 
X9110
D.C. Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 13)
ICC1
ICC2
ISB
VCC Supply Current
(active)
VCC Supply Current
(nonvolatile write)
VCC Current (standby)
ILI
ILO
VIH
VIL
VOL
VOH
VOH
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
Output LOW Voltage
Output HIGH Voltage
Output HIGH Voltage
fSCK = 2.5 MHz, SO = Open, VCC = 5.5V
Other Inputs = VSS
fSCK = 2.5MHz, SO = Open, VCC = 5.5V
Other Inputs = VSS
SCK = SI = VSS, Addr. = VSS,
CS = VCC = 5.5V
VIN = VSS to VCC
VOUT = VSS to VCC
IOL = 3mA
IOH = -1mA, VCC ≥ +3V
IOH = -0.4mA, VCC ≤ +3V
VCC x 0.7
-1
VCC - 0.8
VCC - 0.4
TYP
1
MAX
(Note 13)
400
5
3
10
10
VCC + 1
VCC x 0.3
0.4
UNITS
µA
mA
µA
µA
µA
V
V
V
V
V
Endurance and Data Retention
PARAMETER
Minimum Endurance
Data Retention
MIN
100,000
100
UNITS
Data changes per bit per register
years
Capacitance
SYMBOL
TEST
CIN/OUT (Notes 8, 10) Input/Output Capacitance (SI)
COUT (Note 10)
Output Capacitance (SO)
CIN (Note 10)
Input Capacitance (A0, CS, WP, HOLD, and SCK)
TEST CONDITIONS
VOUT = 0V
VOUT = 0V
VIN = 0V
MAX
8
8
6
UNITS
pF
pF
pF
Power-up Timing
SYMBOL
PARAMETER
MIN
MAX
UNITS
tr VCC (Note 10)
VCC Power-up Rate
0.2 50 V/ms
tPUR (Notes 10, 11) Power-up to Initiation of Read Operation
1 ms
tPUW (Note 11)
Power-up to Initiation of Write Operation
50 ms
NOTES:
10. Limits established by characterization and are not production tested.
11. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued.
12. ESD Rating on RH, RL, RW pins is 1.5kV (HBM, 1.0µA leakage maximum), ESD rating on all other pins is 2.0kV.
13. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
A.C. Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Level
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
11 FN8158.3
February 13, 2008
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet X9110.PDF ] | |
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