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PDF IN16C554A Data sheet ( Hoja de datos )
| Número de pieza | IN16C554A | |
| Descripción | Quadruple UART | |
| Fabricantes | IK Semiconductor | |
| Logotipo |  |
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1. Description
IN16C554A
Quadruple UART
February 2009 REV 1.01
IN16C554A is an enhanced quadruple version of the 16C550UART (Universal
Asynchronous Receiver Transmitter). IN16C554A is in part an upgrade version of
IN16C554, as it is designed for 3.3V only and has AUTO-CTS, AUTO-RTS functions.
In IN16C554A, Each channel can be put into FIFO mode to relieve the CPU of excessive
software overhead. In this mode, internal FIFOs are activated and 16 bytes plus 3 bit of
error data per byte can be stored in both receive and transmit modes.
Each channel performs serial-to-parallel conversion on data characters received from a
peripheral device or a MODEM, and parallel-to-serial conversion on data characters
received from the CPU. The CPU can read the complete status of the UART at any time
during the functional operation. The Status information includes the type and condition of
the transfer operations being performed by the UART, as well as any error conditions
such as parity, overrun, framing, and break interrupt.
IN16C554A includes a programmable baud rate generator which is capable of dividing the
timing reference clock input by divisors of 1 to 216-1, and producing a 16x clock for driving
the internal transmitter logic. Provisions are also included to use this clock to drive the
receiver logic.IN16C554A has complete MODEM-control capability and an interrupt
system that can be programmed to the user’s requirements, minimizing the computing
required to handle the communication links. Moreover IN16C554A can select hardware
flow control. Hardware flow control significantly reduces software overhead and increases
system efficiency.
2. Features
■ In the FIFO mode, Each channel’s transmitter and receiver is buffered with 16-byte
FIFO to reduce the number of interrupts to CPU.
■ Adds or deletes standard asynchronous communication bits (start, stop, parity) to or
from the serial data.
■ Holding Register and Shift Register eliminate need for precise synchronization
between the CPU and serial data.
■ Independently controlled transmit, receive, line status and data interrupts.
■ Programmable Baud Rate Generators which allow division of any input reference
clock by 1 to 216-1 and generate an internal 16X clock.
■ Independent receiver clock input
Modem control functions (CTS#, RTS#, DSR#, DTR#, RI#, and DCD#).
■ Fully programmable serial interface characteristics.
- 5-, 6-, 7-, or 8-bit characters
- Even-, Odd-, or No-Parity bit
1-, 1.5-, 2-Stop bit generation. ( Like other general UARTs, IN16C554 checks only
one stop bit, no matter how many they are)
1
1 page  
IN16C554A
Quadruple UART
February 2009 REV 1.01
5.2 Pin Configuration for 68-Pin PLCC Package
nDSR0
nCTS0
nDTR0
VCC
nRTS0
INT0
nCS0
TXD0
nIOW
TXD1
nCS1
INT1
nRTS1
GND
nDTR1
nCTS1
nDSR1
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10 60
11 59
12 58
13 57
14 56
15 55
16 54
17
18
SB16C554A-PL68
53
52
19 51
20 50
21 49
22 48
23 47
24 46
25 45
26 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
nDSR3
nCTS3
nDTR3
GND
nRTS3
INT3
nCS3
TXD3
nIOR
TXD2
nCS2
INT2
nRTS2
VCC
nDTR2
nCTS2
nDSR2
Figure 3: 68-Pin PLCC Pin Configuration
5
5 Page 
IN16C554A
Quadruple UART
February 2009 REV 1.01
RXD
RTS#
IOR#
START DATA BYTE n-1 STOP
START
DATA BYTE n
STOP
DATA BYTE 1
DATA BYTE 2
START
DATA BYTE n
Figure 5: RTS# Functional Timing
6.1.2 Auto-CTS
Setting MSR [5] to ‘1’ enables Auto-RTS. If enabled, data in TX FIFO are determined to
be transmitted or suspended by the value of CTS#. If ‘0’, it means external UART can
receive new data and data in TX FIFO are transmitted through TXD pin. If ‘1’, it means
external UART can not accept more data and data in TX FIFO are not transmitted. But
data being transmitted by then complete transmission. These procedures are performed
irrespective of FIFO modes. While Auto-CTS is enabled, you can verify the input value of
CTS# by FSR[1]. If ‘0’, CTS# is ‘0’ and it means external UART can accept new data,
If ’1’, CTS# is ‘1’ and it means external UART can not accept more data and data in TX
FIFO are not being transmitted. If IER[7] is set to ‘1’, interrupt is generated by Auto-CTS
when the input of CTS# is changed from ‘0’ to ‘1’, and it is shown on ISR[5:0]. Interrupts
generated by Auto-CTS are removed if MSR is read.
6.2 Programmable Baud Rate Generator
The IN16C554A has a programmable baud rate generator. The baud rate generator
divides this clock frequency by a programmable divisor (DLL and DLM) between 1 and
(216 – 1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate
clock is used by transmitter for data bit shifting and receiver for data sampling.
The divisor of the baud rate generator is:
( )Divisor =
XTAL1 Crystal Input Frequency
(Desired Baud Rate x 16)
XTAL1
XTAL2
INTERNAL
OSCILLATOR
LOGIC
PROGAMMABLE
DIVISOR
BAUD RATE
GENERATOR
LOGIC
INTERNAL
BAUD RATE
CLOCK FOR
TRANSMITTER
AND
RECEIVER
Figure 6: Baud Rate Generator Block Diagram
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IN16C554A.PDF ] | |
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