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PDF ISL1801 Data sheet ( Hoja de datos )
| Número de pieza | ISL1801 | |
| Descripción | sPMIC | |
| Fabricantes | Intersil | |
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sPMIC for Micro Converter Bias and Drivers
ISL1801
The ISL1801 is a power management IC (PMIC) optimized for
solar array micro converters and other systems operating from
a high voltage DC supply. The ISL1801 can be used in buck,
boost or buck-boost microconverter topologies in order to
maximize the energy harvest from a solar array. In addition to
the power stage and main controller, the ISL1801 includes the
bias regulators, gate drivers, current sense amplifier and
comparators needed for micro converters.
The ISL1801 integrates two switching regulators that can be
used to generate the driver and the micro-controller (MCU)
power supplies. In addition, it has a low offset, low drift
amplifier for current sensing, two comparators for overvoltage
and overcurrent protection plus a watchdog timer to reset the
MCU if necessary. This single IC solution offers high integration
and dramatically reduces the total number of components in
the microconverter system improving the system reliability and
reducing cost.
The first regulator takes input voltages ranging from 9V to 90V
from the solar panel and outputs a regulated supply for drivers
and the secondary regulator. The secondary regulator converts
the output of the first regulator to a programmable
micro-controller supply, typically 3.3V. A high voltage start-up
LDO provides the necessary bias voltage until the switching
regulator is operating.
The ISL1801 integrates two high-speed MOSFET drivers for
buck, flyback or boost converters configured as shown in the
application schematics. The Drive3 also has the integrated
peak current limiting capabilities.
The ISL1801 includes comprehensive start-up, shutdown and
fault logic to ensure reliable operation of micro converters in
solar applications.
Features
• 90V input buck switching regulator
- 120mA (minimum) output with OCP, OVP, OTP
- Integrated upper and lower MOSFETs
• 90V on-chip start-up 6.7V LDO
• Low voltage buck switching regulator
- 200mA (minimum) output with OCP, OVP
- Integrated upper and lower MOSFETs
- PGOOD output
• Low voltage bias LDO
- Input voltage range from 6V to 14V
- Regulated 5V output up to 10mA
• Dual high-speed gate driver
- 14V voltage rating
- 2A peak sourcing and 5A peak sinking current
- Peak current limit for DRIVE3
• Dedicated amplifier for accurate current sense
• Two comparators for general purpose protection
• Integrated watchdog timer
Applications
• Solar power optimizer
• Solar power micro-inverter
• Solar charge controller
• Telecom power supply
July 24, 2014
FN8259.1
VIN +
PV MODULE
SENSE
3.3V
ISL1801
CONTROL
PROCESSOR AND/OR
COMMUNICATIONS
FIGURE 1. TYPICAL APPLICATION
VOUT +
VOUT -
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL1801
Pin Descriptions (Continued)
PIN#
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
PIN NAME
DESCRIPTION
RPWM3
The reset signal for both flip-flops in the LATCHRPT circuit and overcurrent-protection circuit of DRIVE3/PHASE3. The
RPWM3=0 will reset both flip-flops. Avoid running PWM3=1 with RPWM3=0 for a long time or at very high frequency, since
it may result in very high switching frequency at DRIVE3 in the overcurrent protection condition.
BCMD Logic input to control BDRIVE.
BRESET Logic input to reset the LATCHRPT flip-flop in the BDRIVE control circuit.
WDI Watchdog circuit clock input signal.
VDDREF Reference signal for output signals to the MCU. Connect this pin to VOUT2, which provides a clamp voltage for all the output
pins (CMP1O, AMPO) interfacing with the MCU.
LATCHRPT Open drain output signal. When either comparator or Phase3 overcurrent protection is triggered, this pin is pulled LOW to
inform the MCU. The two internal flip-flops used to latch these faults can be reset by setting RWPM3=0.
PGOOD2 Open drain output pin indicating power-good for the low voltage regulator. A logic low signal at the watchdog output will also
pull this pin LOW allowing it to reset the MCU in either fault condition.
AMPO Integrated amplifier output.
AMP- Integrated amplifier inverting input.
AMP+ Integrated amplifier non-inverting input.
SGND The ground pin of the sensitive control circuits biased by VCC5V. Connect this pin to a ground plane with minimum noise.
CMP1+ Comparator 1 non-inverting input.
CMP1- Comparator 1 inverting input.
CMP1O Comparator 1 output. This signal also triggers the flip-flop for the LATCHRPT signal.
CMP2- Comparator 2 inverting input.
CMP2+ Comparator 2 non-inverting input.
FB2 The feedback sense pin for the low voltage switching regulator. The output voltage is programmable by a resistor divider
feeding back the output voltage.
TON2
On time adjustment for the secondary (low voltage) switching regulator. Connect a resistor from this pin to the input voltage
of the low voltage regulator to adjust the on time and switching frequency.
PGND2
The ground pin of the low voltage switching regulator’s power stage. There are switching power current pulses coming out of
this pin. Place the ground pad of the input power stage decoupling cap as close to this pin as possible.
PHASE2 The phase node of the low voltage switching regulator. This pin should be connected to the output inductor.
BOOT2
The boot pin of the low voltage switching regulator. An external bootstrap capacitor is required. This pin provides bias voltage
to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive the internal N-channel MOSFET.
The boot diode is included within the IC.
VIN2 Input of the low voltage switching regulator. This pin is connected to the drain of the internal high-side MOSFET.
VCC5V
The output of the internal 5V LDO providing the bias supply for the IC. A 1µF ceramic decoupling capacitor should be placed
from this pin to ground.
GND The analog ground pin.
PRELOAD
Place a resistor from this pin to VOUT1 to provide the loading for the high voltage switching regulator. When this load can be
successfully driven, the low voltage switching regulator will be enabled. If the PV module output power is insufficient, the low
voltage switching regulator will not start.
FB1 The feedback sense pin for the high voltage switching regulator. The output voltage is programmable by a resistor divider
feeding back the output voltage.
TON1
On time adjustment for the high voltage switching regulator. Connect a resistor from this pin to the input voltage of the high
voltage regulator to adjust the on time and switching frequency.
TIMER
Tie a resistor from VCC5V to this pin and a cap from this pin to ground. The RC time constant sets the time needed for both
start-up and watchdog timing. A minimum of 0.01µF should be connected to this pin to filter the switching noise from BOOT1.
The pull-up resistor should not be more than 200kΩ to assure correct operation.
Submit Document Feedback
5
FN8259.1
July 24, 2014
5 Page 
ISL1801
Dual High-Speed Comparator Electrical Specifications TA = +25°C, VR1 = 10V, VR2 = 3.3V. Boldface limits apply
over the operating temperature range, -40°C to +85°C. (Notes 6, 7)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
(Note 6)
MAX
(Note 7)
UNITS
Input Offset Voltage
-5.5 0
5.5 mV
Input Bias Current
±1 pA
Input Offset Current
±1 pA
VCM_min
VCM_max
CMRR
Minimum Common-Mode Voltage
Maximum Common-Mode Voltage
Common-Mode Rejection Ratio
Input Common-Mode Capacitance
VCM = -0.2V to VOUT2
-0.2 V
3.3 V
62 dB
2 pF
Input Differential Capacitance
4 pF
Output High Voltage
Output Low Voltage
Short Circuit Current
IOUT = -0.3mA; VDDREF Tied to 3.3V
VOUT2
2.7
3
V
IOUT = 0.3mA
175 300 mV
1 mA
SWITCHING SPECIFICATIONS
Low-to-High Propagation Delay Time
Input overdrive = 100mV
0.55
µs
High-to-low Propagation Delay Time
Input overdrive = 100mV
0.2 µs
CMP1 Rise Time
CL = 10pF, CMP1+ toggled from 0V to
1V
5
100 550
ns
CMP1 Fall Time
CL = 10pF, CMP1+ toggled from 1V to
0V
5
100 550
ns
LATCHRPT (OPEN DRAIN OUTPUT)
LATCHRPT One-Shot Pulse Width
Under pulse by pulse OC condition,
LATCHRPT pulled low for one-shot
period of each OC cycle
1.1 2.5 µs
LATCHRPT Leakage Current
LATCHRPT Voltage Low
VPULLUP = 3.3V
ILATCHRPT = 4mA
1 µA
0.5 V
Preload Electrical Specifications TA = +25°C, VR1 = 10V, VR2 = 3.3V. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Notes 6, 7)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 7
TYP
(Note 6)
MAX
(Note 7)
UNITS
POWER MOSFET
rDS(ON) Switch 1 ON ON-Resistance
Pull-up to VCC1 = 10V through 100Ω
resistor (Note 8)
242
350
472
Ω
rDS(ON) Switch 2 ON ON-Resistance
Pull-up to VCC1 = 10V through 100Ω
90
120
165
resistor (Note 8)
Ω
rDS(ON) Switch 3 ON ON-Resistance
Pull-up to VCC1 = 10V through 100Ω
40
56
76
Ω
resistor (Note 8)
rDS(ON) Switch 4 ON ON-Resistance
Pull-up to VCC1 = 10V through 100Ω
resistor (Note 8)
8.7
11.4
14.8
Ω
NOTES:
6. Compliance to datasheet values is assured by one or more methods: production test, characterization and/or design.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8. Not production tested.
Submit Document Feedback 11
FN8259.1
July 24, 2014
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISL1801.PDF ] | |
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