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PDF LH28F160S3H-L Data sheet ( Hoja de datos )
| Número de pieza | LH28F160S3H-L | |
| Descripción | 16M-bit (2MB x 8/1MB x 16) Smart 3 Flash Memories | |
| Fabricantes | Sharp | |
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LH28F160S3-L/S3H-L
LH28F160S3-L/S3H-L
DESCRIPTION
The LH28F16S3-L/S3H-L flash memories with
Smart 3 technology are high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications, having high programming
performance is achieved through high-optimized
page buffer operations. Their symmetrically-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for resident flash arrays, SIMMs and
memory cards. Their enhanced suspend
capabilities provide for an ideal solution for code +
data storage applications. For secure code storage
applications, such as networking, where code is
either directly executed out of flash or downloaded
to DRAM, the LH28F160S3-L/S3H-L offer three
levels of protection : absolute protection with VPP at
GND, selective hardware block locking, or flexible
software block locking. These alternatives give
designers ultimate control of their code security
needs. The LH28F160S3-L/S3H-L are conformed
to the flash Scalable Command Set (SCS) and the
Common Flash Interface (CFI) specification which
enable universal and upgradable interface, enable
the highest system/device data transfer rates and
minimize device and system-level implementation
costs.
FEATURES
• Smart 3 technology
– 2.7 V or 3.3 V VCC
– 2.7 V, 3.3 V or 5 V VPP
• High speed write performance
– Two 32-byte page buffers
– 2.7 µs/byte write transfer rate
• Common Flash Interface (CFI)
– Universal & upgradable interface
• Scalable Command Set (SCS)
16 M-bit (2 MB x 8/1 MB x 16) Smart 3
Flash Memories (Fast Programming)
• High performance read access time
LH28F160S3-L10/S3H-L10
– 100 ns (3.3±0.3 V)/120 ns (2.7 to 3.6 V)
LH28F160S3-L13/S3H-L13
– 130 ns (3.3±0.3 V)/150 ns (2.7 to 3.6 V)
• Enhanced automated suspend options
– Write suspend to read
– Block erase suspend to write
– Block erase suspend to read
• Enhanced data protection features
– Absolute protection with VPP = GND
– Flexible block locking
– Erase/write lockout during power transitions
• SRAM-compatible write interface
• User-configurable x8 or x16 operation
• High-density symmetrically-blocked architecture
– Thirty-two 64 k-byte erasable blocks
• Enhanced cycling capability
– 100 000 block erase cycles
– 3.2 million block erase cycles/chip
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases ICC
in static mode
• Automated write and erase
– Command user interface
– Status register
• ETOXTM∗ V nonvolatile flash technology
• Packages
– 56-pin TSOP Type I (TSOP056-P-1420)
Normal bend/Reverse bend
– 56-pin SSOP (SSOP056-P-0600)5
[LH28F160S3-L]
– 64-ball CSP (FBGA064-P-0811)
– 64-pin SDIP (SDIP064-P-0750)
∗ ETOX is a trademark of Intel Corporation.
5 Under development
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
-1-
1 page  
LH28F160S3-L/S3H-L
PIN DESCRIPTION
SYMBOL
TYPE
A0-A20
INPUT
INPUT/
DQ0-DQ15 OUTPUT
CE0#, CE1# INPUT
RP#
OE#
WE#
INPUT
INPUT
INPUT
OPEN
STS DRAIN
OUTPUT
WP#
BYTE#
INPUT
INPUT
VPP SUPPLY
VCC SUPPLY
GND
NC
SUPPLY
NAME AND FUNCTION
ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
A0 : Byte Select Address. Not used in x16 mode (can be floated).
A1-A4 : Column Address. Selects 1 of 16-bit lines.
A5-A15 : Row Address. Selects 1 of 2 048-word lines.
A16-A20 : Block Address.
DATA INPUT/OUTPUTS :
DQ0-DQ7 : Inputs data and commands during CUI write cycles; outputs data during
memory array, status register, query, and identifier code read cycles. Data pins float to
high-impedance when the chip is deselected or outputs are disabled. Data is internally
latched during a write cycle.
DQ8-DQ15 : Inputs data during CUI write cycles in x16 mode; outputs data during
memory array read cycles in x16 mode; not used for status register, query and identifier
code read mode. Data pins float to high-impedance when the chip is deselected, outputs
are disabled, or in x8 mode (BYTE# = VIL). Data is internally latched during a write cycle.
CHIP ENABLE : Activates the device's control logic, input buffers decoders, and sense
amplifiers. Either CE0# or CE1# VIH deselects the device and reduces power
consumption to standby levels. Both CE0# and CE1# must be VIL to select the devices.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP# VIH enables normal operation. When driven VIL, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
OUTPUT ENABLE : Gates the device's outputs during a read cycle.
WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
STS (RY/BY#) : Indicates the status of the internal WSM. When configured in level
mode (default mode), it acts as a RY/BY# pin. When low, the WSM is performing an
internal operation (block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration). STS High Z indicates that the WSM is ready for new commands, block
erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is
suspended or the device is in deep power-down mode. For alternate configurations of
the STATUS pin, see the Configuration command (Table 3 and Section 4.14).
WRITE PROTECT : Master control for block locking. When VIL, locked blocks can not
be erased and programmed, and block lock-bits can not be set and reset.
BYTE ENABLE : BYTE# VIL places device in x8 mode. All data are then input or output
on DQ0-7, and DQ8-15 float. BYTE# VIH places the device in x16 mode , and turns off
the A0 input buffer.
BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCK-
BIT CONFIGURATION POWER SUPPLY : For erasing array blocks, writing bytes or
configuring block lock-bits. With VPP ≤ VPPLK, memory contents cannot be altered. Block
erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an
invalid VPP (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results
and should not be attempted.
DEVICE POWER SUPPLY : Internal detection configures the device for 2.7 V or 3.3 V
operation. To switch from one voltage to another, ramp VCC down to GND and then
ramp VCC to the new voltage. Do not float any power pins. With VCC ≤ VLKO, all write
attempts to the flash memory are inhibited. Device operations at invalid VCC voltage
(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should
not be attempted.
GROUND : Do not float any ground pins.
NO CONNECT : Lead is not internal connected; recommend to be floated.
-5-
5 Page 
LH28F160S3-L/S3H-L
Table 2.1 Bus Operations (BYTE# = VIH)
MODE
NOTE RP# CE0# CE1# OE# WE# ADDRESS VPP DQ0-15 STS
Read
1, 2, 3, 9 VIH VIL VIL VIL VIH
X
X DOUT X
Output Disable
3 VIH VIL VIL VIH VIH
X
X High Z X
VIH VIH
Standby
3 VIH VIH VIL X
X
X
X High Z X
VIL VIH
Deep Power-Down
4
VIL X
X
X
X
X
X High Z High Z
Read Identifier Codes 9
VIH VIL VIL VIL VIH See Fig. 2 X (NOTE 5) High Z
Query
9 VIH VIL VIL VIL VIH See Table 6 X (NOTE 6) High Z
through 10
Write
3, 7, 8, 9 VIH VIL VIL VIH VIL
X
X DIN X
Table 2.2 Bus Operations (BYTE# = VIL)
MODE
NOTE RP# CE0# CE1# OE# WE# ADDRESS VPP DQ0-7 STS
Read
1, 2, 3, 9 VIH VIL VIL VIL VIH
X
X DOUT X
Output Disable
3 VIH VIL VIL VIH VIH
X
X High Z X
VIH VIH
Standby
3 VIH VIH VIL X
X
X
X High Z X
VIL VIH
Deep Power-Down
4
VIL X
X
X
X
X
X High Z High Z
Read Identifier Codes 9
VIH VIL VIL VIL VIH See Fig. 2 X (NOTE 5) High Z
Query
See Table 6
9 VIH VIL VIL VIL VIH
X (NOTE 6) High Z
through 10
Write
3, 7, 8, 9 VIH VIL VIL VIH VIL
X
X DIN X
NOTES :
1. Refer to Section 6.2.3 "DC CHARACTERISTICS".
When VPP ≤ VPPLK, memory contents can be read, but
not altered.
2. X can be VIL or VIH for control pins and addresses, and
VPPLK or VPPH1/2/3 for VPP. See Section 6.2.3 "DC
CHARACTERISTICS" for VPPLK and VPPH1/2/3 voltages.
3. STS is VOL (if configured to RY/BY# mode) when the
WSM is executing internal block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration
algorithms. It is floated during when the WSM is not
busy, in block erase suspend mode with (multi)
word/byte write inactive, (multi) word/byte write suspend
mode, or deep power-down mode.
4. RP# at GND±0.2 V ensures the lowest deep power-
down current.
5. See Section 4.2 for read identifier code data.
6. See Section 4.5 for query data.
7. Command writes involving block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration are
reliably executed when VPP = VPPH1/2/3 and VCC =
VCC1/2.
8. Refer to Table 3 for valid DIN during a write operation.
9. Don’t use the timing both OE# and WE# are VIL.
- 11 -
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