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PDF AN921 Data sheet ( Hoja de datos )

Número de pieza AN921
Descripción Configurable Logic Unit
Fabricantes Silicon Laboratories 
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AN921: Configurable Logic Unit
The EFM8LB1 and EFM8BB3 family of MCUs contain Configura-
ble Logic Units (CLUs) that can be applied to applications that re-
quire some form of programmable logic.
This document demonstrates how to use CLUs to implement the following functions:
• SR latch
• D latch
• Button debounce
• Manchester encoder/decoder
• Biphase Mark encoder/decoder
KEY POINTS
• Configurable Logic operates without CPU
intervention.
• Each unit supports 256 different
combinatorial logic functions, such as
AND, OR, XOR, and multiplexing.
• Multiple units combined can implement
latches, encoders, and decoders.
External Pins
Timer Overflow Pulses
PCA Channels
CLU Asynch Outputs
External Pins
ADC0 ADBUSY Flag
PCA Channels
CLU Asynch Outputs
Carry from CLU[n-1]
(CLU3 carries to CLU0)
SYSCLK
Timer Overflow (ALTCLK)
Input Mux A
Input Mux B
CnEN
CnEN
CnEN
CLUn
Carry to CLU[n+1]
Look
Up
Table
(LUT)
OEN
CnEN
CnEN
DQ
CE
CLR
Q
RST
Output
Selection
SYSCLK
CLUnOUT
Asynchronous Output
(to other CLUs)
CnOUTa
Synchronizer
Synchronous
Output
(to peripherals)
CnOUT
Clock
Polarity
Clock
Selection
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AN921 pdf
AN921: Configurable Logic Unit
D Latch
3. D Latch
Configurable Logic Units can be used to build a D latch. This section shows how this memory circuit can be built without using the D
flip-flop portion of the CLU. This is advantageous in applications where we may want the output of the latch to be sent to another CLU
via the carry input.
3.1 Background
The truth table for a D latch is shown below. When the clock input (CLK) is not rising, the next output (QNEXT) will remain the same as
the current output (Q). When the clock is rising and D input is 0, the next output is 0. When the clock is rising and the D input is 1, the
next output is 1.
Table 3.1. Truth Table of D Latch (Simplified)
CLK
D
Q
QNEXT
Comments
Non-rising
X
X
Q
Hold state
Rising
0
X
0
Clock rising, D = 0
Rising
1
X
1
Clock rising, D = 1
3.2 D Latch Implementation
To implement the D latch, signals D, CLK and Q must be assigned to CLU inputs and outputs. CLK can be assigned to CLU3's MXA
input. The current output Q can be assigned to CLU3's MXB input. The last available input to CLU3 is the Carry, which always the
output of the previous CLU. Therefore, RESET is assigned to CLU2's MXA, and the CLU2 LUT implements a buffer, as shown below.
CLU2
D MXA
CARRY IN
CLK MXA
CLU3
MXB
Q
Figure 3.1. Block Diagram of D Latch
The D latch truth table can now be expanded as shown below. When the rows are ordered as shown, the QNEXT column read from top
to bottom is the binary value, from most-significant bit to least-significant bit, written to the LUT register to implement the SR latch.
Therefore, CLU1FN should be initialized to 0xAC.
Table 3.2. Truth Table of D Latch (Expanded)
CLK (MXA)
1
1
1
1
0
0
0
0
Q (MXB)
1
1
0
0
1
1
0
0
D (CARRY IN)
1
0
1
0
1
0
1
0
QNEXT
1
0
1
0
1
1
0
0
Comments
Clock rising, D = 1
Clock rising, D = 0
Clock rising, D = 1
Clock rising, D = 0
Hold state
Hold state
Hold state
Hold state
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AN921 arduino
AN921: Configurable Logic Unit
Manchester Encoder/Decoder
5.2 Manchester Encoder
In this section, we will demonstrate how to use the CLUs and SPI to combine SPI data and clock signals into a single Manchester-
encoded signal with little CPU intervention.
5.2.1 Manchester Encoder Implementation
The implementation of the Manchester encoder will encode the SPI output into a Manchester-encoded signal. The SPI module signals
for SCK and MOSI are sent to the GPIOs via the priority crossbar decoder, and the CLUs will take these 2 pins as inputs to encode into
Manchester code. The block diagram of the encoder logic is shown below:
CLU0
MOSI
SPI SCK
Priority
Crossbar
Decoder
MOSI
SCK
MXB
MXA
DQ
CLU1
X1 MXB
MXA
SYSCLK
DQ
Manchester
Figure 5.2. Manchester Encoder Block Diagram
The timing diagram of the Manchester encoded signal and the original SPI clock and MOSI data are shown below:
SYSCLK
SCK
MOSI
X1
Manchester
B
A
10
Figure 5.3. Timing Diagram of Manchester Encoder
The implementation is based on SPI configured with low idle state (CKPOL = 0) and data centered on the first edge (CKPHA = 0), the
rising edge in the implementation. The implementation generates a Manchester code where the bit boundary is aligned with the rising
edge of SCK delayed by a half SYSCLK cycle.
In the implementation, CLU0 is used to generate a data bit representation of MOSI that is valid between the rising edges of SCK (X1,
event A). X1 is then XORed with the SCK in CLU0 to generate the Manchester coded signal. If the LUT output of CLU0 was used for
the Manchester code, there would be glitches because the inputs of the XOR gate, SCK, and X1 transition on the same edge. Hence,
this output is clocked by the inverted SYSCLK to avoid glitches. Due to the synchronous design of the SPI block, we know that the
rising edge of SCK will be aligned to the rising edge of SYSCLK. Hence, we can avoid glitches by using the falling edge of SYSCLK to
clock the XOR output (event B).
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