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PDF W15NK50Z Data sheet ( Hoja de datos )

Número de pieza W15NK50Z
Descripción STW15NK50Z
Fabricantes STMicroelectronics 
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No Preview Available ! W15NK50Z Hoja de datos, Descripción, Manual

STP15NK50Z/FP - STB15NK50Z
STB15NK50Z-1 - STW15NK50Z
N-channel 500V - 0.30- 14A TO-220/FP/D2PAK/I2PAK/TO-247
Zener-protected SuperMESH™ Power MOSFET
General features
Type
STP15NK50Z
STP15NK50ZFP
STB15NK50Z
STB15NK50Z-1
STW15NK50Z
VDSS
500V
500V
500V
500V
500V
RDS(on) ID
Pw
<0.3414A 160 W
<0.3414A 40 W
<0.3414A 160W
<0.3414A 160W
<0.3414A 160W
Extremely high dv/dt capability
100% avalanche tested
Gate charge minimized
Very low intrinsic capacitances
Very good manufacturing repeatibility
Description
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage MOSFETs including revolutionary
MDmesh™ products.
Applications
Switching application
3
2
1
TO-220
3
2
1
TO-220FP
123
I2PAK
TO-247
3
1
D2PAK
Internal schematic diagram
Order codes
Part number
STP15NK50Z
STP15NK50ZFP
STB15NK50ZT4
STB15NK50Z
STB15NK50Z-1
STW15NK50Z
January 2007
Marking
P15NK50Z
P15NK50ZFP
B15NK50Z
B15NK50Z
B15NK50Z
W15NK50Z
Rev 4
Package
TO-220
TO-220FP
D2PAK
D2PAK
I2PAK
TO-247
Packaging
Tube
Tube
Tape & reel
Tube
Tube
Tube
1/19
www.st.com
19

1 page




W15NK50Z pdf
STP15NK50Z - STP15NK50ZFP - STB15NK50Z - STB15NK50Z-1 - STW15NK50Z Electrical charac-
2 Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 5. On/off states
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
V(BR)DSS
Drain-source breakdown
voltage
IDSS
Zero gate voltage drain
current (VGS = 0)
IGSS
VGS(th)
RDS(on)
Gate body leakage current
(VDS = 0)
Gate threshold voltage
Static drain-source on
resistance
ID = 1mA, VGS= 0
VDS = Max rating,
VDS = Max rating @125°C
VGS = ±20V
VDS= VGS, ID = 100µA
VGS= 10V, ID= 7A
500
3
1
50
±10
3.75 4.5
0.30 0.34
V
µA
µA
µA
V
Table 6. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
gfs (1) Forward transconductance VDS =15V, ID = 7A
12 S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS =25V, f=1 MHz, VGS=0
2260
264
64
pF
pF
pF
Coss
(2)
eq .
Equivalent output
capacitance
VGS=0, VDS =0V to 400V
150
pF
Qg Total gate charge
Qgs Gate-source charge
Qgd Gate-drain charge
VDD=400V, ID = 14A
VGS =10V
76 106 nC
15 nC
40 nC
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off delay time
Fall time
VDD=250 V, ID=7A,
RG=4.7Ω, VGS=10V
(see Figure 18)
20 ns
23 ns
62 ns
15 ns
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
inceases from 0 to 80% VDSS
5/19

5 Page





W15NK50Z arduino
STP15NK50Z - STP15NK50ZFP - STB15NK50Z - STB15NK50Z-1 - STW15NK50Z Package mechani-
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
11/19

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