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PDF AD6439 Data sheet ( Hoja de datos )

Número de pieza AD6439
Descripción Discrete Multitone (DMT) Coprocessor
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
Discrete Multitone (DMT) Coprocessor
for ADSL Chipsets
AD6439
FEATURES
Component in Analog Devices’ AD20msp918 ADSL
Chipset
Designed to ANSI T1.413 Issue 2/ETSI TR238/ITU
G.992.1 and G.992.2
Higher Performance
Improved Data Rates or Longer Reach
Suitable for CO or Residence (ATU-R and ATU-C)
Performs All DMT Functions and Operations
Trellis Coding
Echo Cancellation
Symmetric Transforms (512 Point)
Flexible Allocation of Tones Upstream/Downstream
Supports Symmetric Services (SDSL)
Increased Upstream (e.g., 1 Mbps)
Supports ADSL Over ISDN (Shifted U/S)
Strict Filters for Spectral Compatibility
128-Lead MQFP
–40؇C to +85؇C, 3.3 V Operation, 1.1 W
GENERAL DESCRIPTION
The AD6439 Discrete Multitone (DMT) Coprocessor is part of
Analog Devices ADSL solution, a series of flexible, standards-
based chipsets for creating high performance ADSL and SDSL
modems that implement a superset of standard Category 2
functionality.
A high performance alternative to the AD6436 DMT Coprocessor,
the AD6439 meets the functionality requirements of ANSI
T1.413 Category 2 (trellis coding, echo cancellation), but is
considerably more versatile. It implements both transmit and
receive paths (trellis coding/decoding, IFFT/FFT, filtering and
echo cancellation). Symmetric transforms allow flexible alloca-
tion of upstream and downstream bandwidth, including sym-
metric data rates. Improved digital filters exceed the requirements
of T1.413 and deliver strict spectral masks (e.g., for VDSL
compatibility).
FUNCTIONAL BLOCK DIAGRAM
AD6435 TX SERIAL
OR
AD6436
INTERFACE
FRAMER
RX SERIAL
TRELLIS
ENCODE/
DECODE
IFFT
512/512PT
IFFT
512/512PT
DIGITAL FILTER
TX PATH
FILTERS
EC
RX PATH
FILTERS
16
DAC
AD6440
OR
AD6437
16
ADC
DSP PORT
CONTROL LOGIC
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999

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AD6439 pdf
WRITE OPERATION
Parameter Description
Switching Characteristics:
tDW
tDH
tWP
tASW
tDDR
tCWR
tAW
tWRA
tWWR
Data Setup Before NWR High
Data Hold After NWR High
NWR Pulsewidth
A0–A13, NCS Setup Before NWR Low
Data Disable Before NWR or NRD Low
DSP_CLK High to NWR Low
A0–A13, NCS Setup Before NWR Deasserted
A0–A13, NCS Hold After NWR Deasserted
NWR High to NRD or NWR Low
NOTES
W = wait state x (DSP_CLK period).
AD6439 accesses faster than 20 MHz (DSP_CLK) requires one wait state.
Min
10 + W
6
12 + W
2
1
3
12 + W
5
12
DSP_CLK
A0–A13
NCS
NWR
D
NRD
tASW
tCWR
tWP
tAW
tWRA
tWWR
tDH tDDR
tDW
Figure 6. Write Operation
AD6439
Max Units
ns
ns
ns
ns
ns
16 ns
ns
ns
ns
REV. 0
–5–

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AD6439 arduino
AD6439
Because of the direction of the clock skew, this protocol allows
up to one full cycle of skew less some period for settling round
trip timing (AD6439 to AD6435/AD6438 and back, or vice-
versa). The main difference from the TX path is that the data
and RX_BS are sampled by the AD6435/AD6438 on the falling
clock edge because of the known direction of clock skew. The
time from data request to Bit 7 being received is only one clock
(assuming the AD6439 has data ready), so even for the worst
case of 9 clocks per byte, the time to transmit a full frame is less
than 97 µs, which should be within the safe window for the
AD6439.
The RX_FRAME signal, which is not shown, is output by the
AD6439 on the rising edge of TX_RX_SCLK to indicate the
start of a frame. The AD6435/AD6438 does not raise the
RX_DREQ line before the start of a frame, or after the number
of data bytes programmed by the DSP has been received within
a frame.
DAC Interface
The AD6439 provides 16 bits (TX[15:0]) to a Tx A/D con-
verter and 16 bits (AEC[15:0]) to the AEC A/D (see Figure 8
for the location of this block and Figure 11 for signal timing).
These two buses are muxed onto one 16-bit output bus provided
to the analog front end (AD6437, AD6440). The TX_CLK
signal accompanying the 16-bit data bus qualifies TX and AEC
data.
The output bus always provides valid tx sample data on the
rising edge of TX_CLK and valid AEC sample data on the
falling of TX_CLK. During normal operation, the TX and AEC
output sample rates are 17.664 MHz, therefore, on the output
data bus, the rate is 35.328 MHz and TX_CLK is 17.664 MHz.
TX and AEC data can be down sampled to 8.832 MHz, in
which case the output data bus has a rate of 17.664 MHz and
the TX_CLK signal is 8.832 MHz. The TX Int8 and AEC Int8
blocks can also be bypassed, making the TX and AEC data rate
only 2.208 MHz, the output bus rate 4.416 MHz and the
TX_CLK signal 2.208 MHz. Data sent out is unsigned, how-
ever the AD6439 can be programmed to send out twos comple-
ment binary data.
Note that TX and AEC paths must always be in the same mode.
They are either both in normal mode, both in downsample
mode, or both in bypass mode.
ADC Interface
The AD6439 includes an interface that accepts 16 bits (RX[15:0])
from an A/D converter (see Figure 8 for the location of this
block). The sample rate is 8.832 MHz, but if the Dec4 block is
bypassed, the rate is only 2.208 MHz. Signal RX_CLK qualifies
when the A/D converter needs to provide valid data. The AD6439
normally assumes that input data is in unsigned binary format,
however, it can also be programmed to received twos comple-
ment binary data.
DSP Port
The AD6439 includes a DSP port consisting of a 14-bit address
bus A[13:0], a 16-bit data bus D[15:0], three bus control pins,
NRD, NWR, NCS, and a clock, DSP_CLK. (See Figure 8 for
the location of this block and Figure 12 for signal details). The
DSP port allows a 2183 DSP to access the AD6439.
ADDR[13:0]
DATA[15:0]
ADSP-2183
DSP_CLK
IOMSN
RDN
WRN
ADDR[13:0]
DATA[15:0]
AD6439
DSP_CLK
CSN
RDN
WRN
Figure 12. ADSP-2183 AD6439 Interface
PIN DESCRIPTION
The AD6439 carries 79 signal pins (24 output pins, 39 input
pins, and 16 bidirectional pins) and 43 supply pins. See Figure
13 (Functional Diagram), Pin Configuration and Pin Function
Description) for details.
TX_DREQ
TX_BS
TX_SDATA
TX_FRM
TX_RX_SCLK
RX_DREQ
RX_BS
RX_SDATA
RX_FRM
AD6439
TX_AEC[15:0]
TX_CLK
RX[15:0]
RX_CLK
MCLK
NRESET
Figure 13. Functional Pin Diagram
35.328MHZ
TX_CLK
TX_AEC[15:0]
AEC0 TX0 AEC1 TX1 AEC2 TX2 AEC3 TX3
Figure 11. TX_AEC Mux Bus in Normal Operation
REV. 0
–11–

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