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PDF AD6440 Data sheet ( Hoja de datos )

Número de pieza AD6440
Descripción Analog Front End
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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a
FEATURES
Complete Analog Front End for ADSL Modems
Part of ADI ADSL Chipset (AD20msp930)
Designed to ANSI T1.413/ETSI TR238/ITU G.adsl
Performance
e.g., 6.1 Mbps Downstream Over 12K Ft.
Suitable for CO or CPE (ATU-C and ATU-R)
Includes Transmit and Receive Signal Paths:
DAC: 20 MSPS 14-Bit Current Output
ADC: 10 MSPS 12-Bit
PGA: –6 dB–30 dB of Gain with 1 dB Steps
Programmable Filters
8-Bit Auxiliary DAC for Timing Recovery
Interface to 3.3 V or 5 V Digital Logic
Low Power Consumption (525 mW)
80-Lead MQFP
–40؇C to +85؇C Operation
Analog Front End for ADSL
AD6440
GENERAL DESCRIPTION
The AD6440 is a complete analog front end IC (AD6440) for
ADSL systems. Although part of the Analog Devices DMT
chipset, it is suitable for use with digital implementations from
other suppliers.
As part of the AD20msp930 chipset, it complements the
AD6449; together with the line driver and an external filter,
they make a complete ADSL datapump, designed to comply
with ANSI and ETSI standards for DMT-based ADSL.
The AD6440 includes both transmit and receive paths. These
include the DAC (up to 20 MSPS, allowing for oversampling of
the downstream transmit signal), ADC (up to 10 MSPS), low
noise PGA and filters. The filters are software configurable for
both the CO and RT modes. There is an 8-bit auxiliary DAC
(e.g., for timing recovery).
The AD6440 has been designed to be versatile, and most blocks
can be used or externally bypassed.
TX[13:0]
14
CPORT
4
VCXO
RX[11:0]
12
FUNCTIONAL BLOCK DIAGRAM
TX DAC OUT AEC DAC OUT
22
AEC FIL IN TX FIL IN
22
14
MUX 14
14-BIT
DAC
14-BIT
DAC
CONTROL
LOGIC
8-BIT
DAC
12-BIT
ADC
AD6440 (AFIC+)
BUF
A = 0, 8dB
A = 0, 8dB
A = 0, –6, –12dB
ANALOG
FILTER
A = 0, –6, –12dB
ANALOG
FILTER
2
TX FIL OUT
TO
LINE DRIVER
2
AEC FIL OUT
TO
HYBRID
ANALOG
FILTER
2
PGA/EQ
A = –6 TO +30dB,
BOOST = 0 – 20dB
@1.1MHz
2
PGA IN
FROM
HYBRID
2
RX ADC IN
RX FIL OUT
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999

1 page




AD6440 pdf
AD6440
Pin Name
TX_AEC[13:0]
TX_CLK
CS[1:0]
AGND
AVDD
TX_FIL_OUT[A,B]
TX_IBIAS, TX_COMP
TX_FSADJ
TX_FIL_IN[A,B]
TX_DAC_OUT[A,B]
DGND
DVDD_5V
AEC_DAC_OUT[A,B]
AEC_FIL_IN[A,B]
AEC_IBIAS, AEC_COMP
AEC_FSADJ
AEC_FIL_OUT[A,B]
RX_ADC_IN[A,B]
RX_FIL_OUT [B,A]
RX_PGA_IN[A,B]
EXT_DRV_PD
RX_REFB, RX_REFT
RX_REFGND
RX_VREF
RX_CML
RX[11:0]
DVDD_3V
Pin #
1–9, 75–79
10
11, 12
13, 30, 37, 51
14, 29, 38, 52
15, 16
17, 21
18
19, 20
23, 22
24, 59, 70
25, 69
26, 27
32, 31
33, 28
34
36, 35
39, 40
41, 42
43, 44
45
46, 47
48
49
50
53–58, 61–66
60, 80
DR
RX CLK
DT
SCLK
TFS
TR_DAC_OUT
67
68
71
72
73
74
PIN FUNCTION DESCRIPTIONS
Description
Digital Data to Tx DAC and AEC DAC.
Clock Signal Used to Validate Transmit Data.
Defines Chip Address.
Analog Ground.
+5 V Analog Supply.
Differential Output from Transmit LPF.
Decoupling Pins for Internal Nodes.
Resistor to AGND.
Differential Input to Transmit LPF.
Complementary Current Outputs.
Digital Ground.
+5 V Digital Supply for Converters. Must Be Connected to 5 V.
Complimentary Current Outputs.
Differential Input to Echo LPF.
Decoupling Pins for Internal Nodes.
Resistor to AGND.
Differential Output from Echo LPF.
Differential Input to ADC.
Differential Output of Rx LPF Filter.
Differential Input to PGA.
Test Pin.
Decoupling Pins for ADC Reference.
External Voltage Reference Ground.
External Voltage Reference.
Common-Mode Level.
Digital Output (Receive) Data from ADC.
Digital Supply for Interface. Can Be Connected to 3.3 V or 5 V to Suit
Different Digital Circuitry.
Serial Data Output. Used to Read Data Written to Registers.
Clock Input Qualifying ADC Data.
Serial Data Input to Timing Recovery DAC.
Clock for Timing Recovery DAC Serial Data.
Frame Sync for Timing Recovery DAC Data.
Voltage Output from Timing Recovery DAC.
REV. 0
–5–

5 Page





AD6440 arduino
S1 S2
S4
ANALOG INPUT
tC
S3
tCH tCL
INPUT CLOCK
RCVCK
OUTPUT DATA
RX[0:11]
t OD
DATA1
Figure 6. Receive Interface Timing Diagram
Symbol
tC
tCH
tCL
tOD
Latency
Table IX. Receive Switching Specifications
Parameter
Clock Period
CLOCK Pulsewidth High
CLOCK Pulsewidth Low
Output Delay
Pipeline Delay
Min Typ Max
100
45
45
8 13
33
104
19
3
Units
ns
ns
ns
ns
Cycles
AD6440
DRIVE
EDGE
SCLK
SFRAME
t RD
SDATA_IN
t SCLKW
t RH
t SCDV
SAMPLE
EDGE
VALID DATA
t SCDH
Symbol
tSCLKW
tRD
tRH
tSCDV
tSCDH
Figure 7. ADSP-2183 Timing
Table X. ADSP-2183 Timing Parameters
External Clock
Switching Characteristics
Clock Period (13.248 MHz)
SFRAME Delay After SCLK
SFRAME Hold After SCLK
SCLK High to SDATA Valid
Transmit Data Hold After SCLK
Typ Min
76
0
0
Max
15
15
Units
ns
ns
ns
ns
ns
REV. 0
–11–

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