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PDF PCU9656 Data sheet ( Hoja de datos )
| Número de pieza | PCU9656 | |
| Descripción | 24-bit UFm 5MHz I2C-bus 100mA 40V LED driver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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PCU9656
24-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
Rev. 1 — 8 December 2011
Product data sheet
1. General description
The PCU9656 is a UFm I2C-bus controlled 24-bit LED driver optimized for voltage switch
dimming and blinking 100 mA Red/Green/Blue/Amber (RGBA) LEDs. Each LEDn output
has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller that
operates at 97 kHz (typical) with a duty cycle that is adjustable from 0 % to 99.6 % to
allow the LED to be set to a specific brightness value. An additional 8-bit resolution (256
steps) group PWM controller has both a frequency of 190 Hz and an adjustable frequency
between 24 Hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 %
to 99.6 % that is used to either dim or blink all LEDs with the same value.
Each LEDn output can be off, on (no PWM control), set at its individual PWM controller
value or at both individual and group PWM controller values. The PCU9656 operates with
a supply voltage range of 2.3 V to 5.5 V and the 100 mA open-drain outputs allow
voltages up to 40 V for the LED supply.
The PCU9656 is one of the first LED controller devices in a new Ultra Fast-mode (UFm)
family. UFm devices offer higher frequency (up to 5 MHz).
The active LOW Output Enable input pin (OE) blinks all the LEDn outputs and can be
used to externally PWM the outputs, which is useful when multiple devices need to be
dimmed or blinked together without using software control.
Software programmable LED Group and three Sub Call I2C-bus addresses allow all or
defined groups of PCU9656 devices to respond to a common I2C-bus address, allowing
for example, all red LEDs to be turned on or off at the same time or marquee chasing
effect, thus minimizing I2C-bus commands. Six hardware address pins allow up to
64 devices on the same bus.
The Software Reset (SWRST) Call allows the master to perform a reset of the PCU9656
through the I2C-bus, identical to the Power-On Reset (POR) that initializes the registers to
their default state causing the output NAND FETs to be OFF (LED off). This allows an
easy and quick way to reconfigure all device registers to the same condition.
A new feature to control LEDn output pattern is incorporated in the PCU9656. A new
control byte called ‘Chase Byte’ allows enabling or disabling of selective LEDn outputs
depending on the value of the Chase Byte. This feature greatly reduces the number of
bytes to be sent to the PCU9656 when repetitive patterns need to be displayed as in
creating a marquee chasing effect.
1 page  
NXP Semiconductors
PCU9656
24-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
Table 2.
Symbol
LED11
A5
n.c.
OE
LED12
LED13
LED14
LED15
LED16
LED17
LED18
LED19
USCL
USDA
VDD
LED20
LED21
LED22
LED23
A0
A1
Pin description …continued
Pin Type
20 O
22 I
23 I
24 I
26 O
27 O
28 O
29 O
32 O
33 O
34 O
35 O
38 I
39 I
40 power supply
41 O
42 O
43 O
44 O
46 I
47 I
Description
LED driver 11
address input 5
do not connect; reserved input
active LOW output enable for LEDs
LED driver 12
LED driver 13
LED driver 14
LED driver 15
LED driver 16
LED driver 17
LED driver 18
LED driver 19
UFm serial clock line
UFm serial data line
supply voltage
LED driver 20
LED driver 21
LED driver 22
LED driver 23
address input 0
address input 1
PCU9656
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 December 2011
© NXP B.V. 2011. All rights reserved.
5 of 45
5 Page 
NXP Semiconductors
PCU9656
24-bit UFm 5 MHz I2C-bus 100 mA 40 V LED driver
7.3.1 Mode register 1, MODE1
Table 5. MODE1 - Mode register 1 (address 00h) bit description
Legend: * default value.
Bit Symbol
Access
Value Description
7 AIF
not user
0
programmable 1*
Register Auto-Increment disabled.
Register Auto-Increment enabled (write default logic 1).
6 AI1
W
0* Auto-Increment bit 1 = 0. Auto-increment range as defined in Table 3.
1 Auto-Increment bit 1 = 1. Auto-increment range as defined in Table 3.
5 AI0
W
0* Auto-Increment bit 0 = 0. Auto-increment range as defined in Table 3.
1 Auto-Increment bit 0 = 1. Auto-increment range as defined in Table 3.
4 SLEEP
W
0 Normal mode[1].
1* Low power mode. Oscillator off[2].
3 SUB1
W
0* PCU9656 does not respond to I2C-bus subaddress 1.
1 PCU9656 responds to I2C-bus subaddress 1.
2 SUB2
W
0* PCU9656 does not respond to I2C-bus subaddress 2.
1 PCU9656 responds to I2C-bus subaddress 2.
1 SUB3
W
0* PCU9656 does not respond to I2C-bus subaddress 3.
1 PCU9656 responds to I2C-bus subaddress 3.
0 ALLCALL W
0 PCU9656 does not respond to LED All Call I2C-bus address.
1* PCU9656 responds to LED All Call I2C-bus address.
[1] It takes 500 s max. for the oscillator to be up and running once SLEEP bit has been set to logic 1. Timings on LEDn outputs are not
guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 s window.
[2] No blinking or dimming is possible when the oscillator is off.
7.3.2 Mode register 2, MODE2
Table 6. MODE2 - Mode register 2 (address 01h) bit description
Legend: * default value.
Bit Symbol
Access
Value Description
7-
not user
programmable
0*
reserved, write must always be a logic 0
6-
not user
programmable
0*
reserved, write must always be a logic 0
5 DMBLNK
W
0* group control = dimming.
1 group control = blinking.
4 INVRT
W
0* reserved, write must always be a logic 0
3 OCH
W
0* outputs change on STOP command[1]
1 outputs change on ninth clock cycle (SCL)
2-
W
1* reserved, write must always be a logic 1
1-
W
0* reserved, write must always be a logic 0
0-
W
1* reserved, write must always be a logic 1
[1] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCU9656. Applicable to registers from
02h (PWM0) to 22h (LEDOUT) only.
PCU9656
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 December 2011
© NXP B.V. 2011. All rights reserved.
11 of 45
11 Page | ||
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