|
|
PDF PCU9655 Data sheet ( Hoja de datos )
| Número de pieza | PCU9655 | |
| Descripción | 16-channel UFm 5MHz bus 100mA 40V LED driver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PCU9655 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
PCU9655
16-channel UFm 5 MHz bus 100 mA 40 V LED driver
Rev. 2 — 2 October 2012
Product data sheet
1. General description
The PCU9655 is a UFm I2C-bus controlled 16-channel LED driver optimized for voltage
switch dimming and blinking 100 mA Red/Green/Blue/Amber (RGBA) LEDs. Each LED
output has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller
that operates at approximately 31.25 kHz with a duty cycle that is adjustable from 0 % to
99.6 % to allow the LED to be set to a specific brightness value. An additional 8-bit
resolution (256 steps) group PWM controller has both a fixed frequency of about 122 Hz
and an adjustable frequency roughly between 15 Hz to once every 16.8 seconds with a
duty cycle that is adjustable from 0 % to 99.6 % that is used to either dim or blink all LEDs
with the same value.
Each LED output can be off, on (no PWM control), set at its individual PWM controller
value or at both individual and group PWM controller values. The PCU9655 operates with
a supply voltage range of 3 V to 5.5 V and the 100 mA open-drain outputs allow voltages
up to 40 V.
The PCU9655 is one of the first LED controller devices in a new Ultra Fast mode (UFm)
family. UFm devices offer higher frequency (up to 5 MHz).
Software programmable LED Group and three Sub Call I2C-bus addresses allow all or
defined groups of PCU9655 devices to respond to a common I2C-bus address, allowing
for example, all red LEDs to be turned on or off at the same time, thus minimizing I2C-bus
commands. On power-up, PCU9655 will have a unique Sub Call address to identify it as a
16-channel LED driver. This allows mixing of devices with different channel widths. Five
hardware address pins on PCU9655 allow up to 32 devices on the same bus.
The Software Reset (SWRST) function allows the master to perform a reset of the
PCU9655 through the I2C-bus, identical to the Power-On Reset (POR) that initializes the
registers to their default state causing the output voltage switches to be OFF (LED off).
This allows an easy and quick way to reconfigure all device registers to the same
condition.
Additionally, a thermal shutdown feature protects the device when the internal junction
temperature exceeds the overtemperature threshold.
1 page  
NXP Semiconductors
PCU9655
16-channel UFm 5 MHz bus 100 mA 40 V LED driver
Table 2.
Symbol
LED11
LED12
LED13
LED14
LED15
RESET
n.c.
USCL
USDA
VDD
Pin description …continued
Pin
PCU9655PW PCU9655PW1
18 19
20 20
21 21
22 22
23 23
25 -
- 24, 25
26 26
27 27
28 28
Type
O
O
O
O
O
I
-
I
I
power supply
Description
LED driver 11
LED driver 12
LED driver 13
LED driver 14
LED driver 15
active LOW reset input
do not connect; reserved input
UFm serial clock line
UFm serial data line
supply voltage
[1] In order to obtain the best system level ESD performance, a standard pull-up resistor (10 k typical) is
required for any address pin connecting to VDD. For additional information on system level ESD
performance, please refer to application notes AN10897 and AN11131.
7. Functional description
Refer to Figure 1 “Block diagram of PCU9655PW”.
7.1 Device addresses
Following a START condition, the bus master must output the address of the slave it is
accessing.
For PCU9655 there are a maximum of 32 possible programmable addresses using the
five hardware address pins A[4:0].
7.1.1 Regular UFm I2C-bus slave address
The I2C-bus slave address of the PCU9655 is shown in Figure 3. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW externally.
Remark: Reserved I2C-bus addresses must be used with caution since they can interfere
with:
• ‘reserved for future use’ I2C-bus addresses (0000 011, 1111 1XX)
• slave devices that use the 10-bit addressing scheme (1111 0XX)
• slave devices that are designed to respond to the General Call address (0000 000)
• High-speed mode (Hs-mode) master code (0000 1XX)
PCU9655
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 2 October 2012
© NXP B.V. 2012. All rights reserved.
5 of 37
5 Page 
NXP Semiconductors
PCU9655
16-channel UFm 5 MHz bus 100 mA 40 V LED driver
7.3.3 LEDOUT0 to LEDOUT3, LED driver output state
Table 7. LEDOUT0 to LEDOUT3 - LED driver output state registers (address 02h to 05h)
bit description
Legend: * default value.
Address Register Bit Symbol Access Value
Description
02h LEDOUT0 7:6 LDR3 W only 00*
LED3 output state control
5:4 LDR2
W only 00*
LED2 output state control
3:2 LDR1
W only 00*
LED1 output state control
1:0 LDR0
W only 00*
LED0 output state control
03h LEDOUT1 7:6 LDR7 W only 00*
LED7 output state control
5:4 LDR6
W only 00*
LED6 output state control
3:2 LDR5
W only 00*
LED5 output state control
1:0 LDR4
W only 00*
LED4 output state control
04h
LEDOUT2 7:6 LDR11
W only 00*
LED11 output state control
5:4 LDR10
W only 00*
LED10 output state control
3:2 LDR9
W only 00*
LED9 output state control
1:0 LDR8
W only 00*
LED8 output state control
05h
LEDOUT3 7:6 LDR15
W only 00*
LED15 output state control
5:4 LDR14
W only 00*
LED14 output state control
3:2 LDR13
W only 00*
LED13 output state control
1:0 LDR12
W only 00*
LED12 output state control
LDRx = 00 — LED driver x is off (default power-up state).
LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking
not controlled).
LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx
register.
LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be
controlled through its PWMx register and the GRPPWM registers.
7.3.4 GRPPWM, group duty cycle control
Table 8. GRPPWM - Group brightness control register (address 08h) bit description
Legend: * default value
Address Register Bit Symbol Access Value
Description
08h GRPPWM 7:0 GDC[7:0] W only 1111 1111* GRPPWM register
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 122 Hz fixed
frequency signal is superimposed with the 31.25 kHz individual brightness control signal.
GRPPWM is then used as a global brightness control allowing the LED outputs to be
dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the 16 outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3
registers).
PCU9655
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 2 October 2012
© NXP B.V. 2012. All rights reserved.
11 of 37
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PCU9655.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PCU9654 | 8-bit UFm 5MHz I2C-bus 100mA 40V LED driver | NXP Semiconductors |
| PCU9655 | 16-channel UFm 5MHz bus 100mA 40V LED driver | NXP Semiconductors |
| PCU9656 | 24-bit UFm 5MHz I2C-bus 100mA 40V LED driver | NXP Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |