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PDF W94AD2KB Data sheet ( Hoja de datos )
| Número de pieza | W94AD2KB | |
| Descripción | 1Gb Mobile LPDDR | |
| Fabricantes | Winbond | |
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W94AD6KB / W94AD2KB
1Gb Mobile LPDDR
Table of Contents-
1. GENERAL DESCRIPTION .................................................................................................................................4
2. FEATURES ........................................................................................................................................................4
3. ORDER INFORMATION ....................................................................................................................................5
4. BALL CONFIGURATION....................................................................................................................................6
4.1 Ball Assignment: LPDDR x16 ...............................................................................................................6
4.2 Ball Assignment: LPDDR x32 ...............................................................................................................6
5. BALL DESCRIPTION .........................................................................................................................................7
5.1 Signal Descriptions...............................................................................................................................7
5.2 Addressing Table..................................................................................................................................8
6. BLOCK DIAGRAM..............................................................................................................................................9
6.1 Block Diagram ......................................................................................................................................9
6.2 Simplified State Diagram ....................................................................................................................10
7. FUNCTIONAL DESCRIPTION .........................................................................................................................11
7.1 Initialization.........................................................................................................................................11
7.1.1 Initialization Flow Diagram....................................................................................................12
7.1.2 Initialization Waveform Sequence ........................................................................................13
7.2 Mode Register Set Operation .............................................................................................................13
7.3 Mode Register Definition ....................................................................................................................14
7.3.1 Burst Length .........................................................................................................................14
7.3.2 Burst Definition .....................................................................................................................15
7.3.3 Burst Type ............................................................................................................................16
7.3.4 Read Latency .......................................................................................................................16
7.4 Extended Mode Register Description .................................................................................................16
7.4.1 Extended Mode Register Definition ......................................................................................17
7.4.2 Partial Array Self Refresh .....................................................................................................17
7.4.3 Automatic Temperature Compensated Self Refresh ............................................................17
7.4.4 Output Drive Strength...........................................................................................................17
7.5 Status Register Read .........................................................................................................................18
7.5.1 SRR Register Definition........................................................................................................18
7.5.2 Status Register Read Timing Diagram .................................................................................19
7.6 Commands .........................................................................................................................................20
7.6.1 Basic Timing Parameters for Commands .............................................................................20
7.6.2 Truth Table – Commands..................................................................................................20
7.6.3 Truth Table - DM Operations................................................................................................21
7.6.4 Truth Table – CKE.............................................................................................................21
7.6.5 Truth Table - Current State Bank n - Command to Bank n...................................................22
7.6.6 Truth Table - Current State Bank n, Command to Bank m ...................................................23
8. OPERATION ....................................................................................................................................................25
8.1 Deselect .............................................................................................................................................25
8.2 No Operation ......................................................................................................................................25
8.2.1 NOP Command ....................................................................................................................25
8.3 Mode Register Set..............................................................................................................................26
8.3.1 Mode Register Set Command ..............................................................................................26
8.3.2 Mode Register Set Command Timing...................................................................................26
Publication Release Date: Oct. 02, 2014
Revision: A01-005
-1-
1 page  
W94AD6KB / W94AD2KB
3. ORDER INFORMATION
PART NUMBER
W94AD6KBHX5I
W94AD6KBHX5E
W94AD2KBJX5I
W94AD2KBJX5E
W94AD6KBHX6I
W94AD6KBHX6E
W94AD2KBJX6I
W94AD2KBJX6E
VDD/VDDQ
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
I/O WIDTH
16
16
32
32
16
16
32
32
TYPE
60VFBGA
60VFBGA
90VFBGA
90VFBGA
60VFBGA
60VFBGA
90VFBGA
90VFBGA
OTHERS
200MHz, -40°C~85°C
200MHz, -25°C~85°C
200MHz, -40°C~85°C
200MHz, -25°C~85°C
166MHz, -40°C~85°C
166MHz, -25°C~85°C
166MHz, -40°C~85°C
166MHz, -25°C~85°C
Publication Release Date: Oct. 02, 2014
Revision: A01-005
-5-
5 Page 
W94AD6KB / W94AD2KB
7. FUNCTIONAL DESCRIPTION
7.1 Initialization
LPDDR SDRAM must be powered up and initialized in a predefined manner. Operations procedures
other than those specified may result in undefined operation. If there is any interruption to the device
power, the initialization routine should be followed. The steps to be followed for device initialization are
listed below.
The Mode Register and Extended Mode Register do not have default values. If they are not
programmed during the initialization sequence, it may lead to unspecified operation. The clock stop
feature is not available until the device has been properly initialized from Step 1 through 11.
Step 1: Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be
brought up simultaneously to prevent device latch-up. Although not required, it is
recommended that VDD and VDDQ are from the same power source. Also assert and hold
Clock Enable (CKE) to a LVCMOS logic high level.
Step 2: Once the system has established consistent device power and CKE is driven high, it is safe
to apply stable clock.
Step 3: There must be at least 200μS of valid clocks before any command may be given to the
DRAM. During this time NOP or DESELECT commands must be issued on the command
bus.
Step 4: Issue a PRECHARGE ALL command.
Step 5: Provide NOPs or DESELECT commands for at least tRP time.
Step 6: Issue an AUTO REFRESH command followed by NOPs or DESELECT command for at
least tRFC time. Issue the second AUTO REFRESH command followed by NOPs or
DESELECT command for at least tRFC time. Note as part of the initialization sequence
there must be two Auto Refresh commands issued. The typical flow is to issue them at
Step 6, but they may also be issued between steps 10 and 11.
Step 7: Using the MRS command, program the base mode register. Set the desired operation
modes.
Step 8: Provide NOPs or DESELECT commands for at least tMRD time.
Step 9: Using the MRS command, program the extended mode register for the desired operating
modes. Note the order of the base and extended mode register programmed is not
important.
Step 10: Provide NOP or DESELECT commands for at least tMRD time.
Step 11: The DRAM has been properly initialized and is ready for any valid command.
- 11 -
Publication Release Date: Oct. 02, 2014
Revision: A01-005
11 Page | ||
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