DataSheet.es    


PDF W967D6HB Data sheet ( Hoja de datos )

Número de pieza W967D6HB
Descripción CellularRAM
Fabricantes Winbond 
Logotipo Winbond Logotipo



Hay una vista previa y un enlace de descarga de W967D6HB (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! W967D6HB Hoja de datos, Descripción, Manual

W967D6HB
1. GENERAL DESCRIPTION
128Mb Async./Page,Syn./Burst CellularRAM
Winbond CellularRAM™ products are high-speed, CMOS pseudo-static random access memories developed for
low-power, portable applications. The device has a DRAM core organized. These devices include an industry-
standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-
power SRAM or Pseudo SRAM offerings.
To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a transparent self refresh
mechanism. The hidden refresh requires no additional support from the system memory controller and has no
significant impact on device READ/WRITE performance.
Two user-accessible control registers define device operation. The Bus Configuration Register (BCR) defines how
the CellularRAM device interacts with the system memory bus and is nearly identical to its counterpart on burst
mode Flash devices. The Refresh Configuration Register (RCR) is used to control how refresh is performed on the
DRAM array. These registers are automatically loaded with default settings during power-up and can be updated
anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh. CellularRAM products
include three mechanisms to minimize standby current. Partial array refresh (PAR) enables the system to limit
refresh to only that part of the DRAM array that contains essential data. Temperature compensated refresh (TCR)
uses an on-chip sensor to adjust the refresh rate to match the device temperaturethe refresh rate decreases at
lower temperatures to minimize current consumption during standby. Deep power-down (DPD) enables the system
to halt the refresh operation altogether when no vital information is stored in the device. The system configurable
refresh mechanisms are accessed through the RCR.
This CellularRAM device is compliant with the industry-standard CellularRAM 1.5 generation feature set established
by the CellularRAM Workgroup. It includes support for both variable and fixed latency, with 3 output-device drive-
strength settings, additional wrap options, and a device ID register (DIDR).
2. FEATURES
•Supports asynchronous, page, and burst operations
• VCC, VCCQ Voltages:
1.7V1.95V VCC
1.7V1.95V VCCQ
• Random access time: 70ns
• Burst mode READ and WRITE access:
4, 8, 16, or 32 words, or continuous burst
Burst wrap or sequential
Max clock rate: 133 MHz (tCLK = 7.5ns)
• Page mode READ access:
Sixteen-word page size
Interpage READ access: 70ns
Intrapage READ access: 20ns
• Low-power features
On-chip temperature compensated refresh (TCR)
Partial array refresh (PAR)
Deep power-down (DPD) mode
Package: 54 Ball VFBGA
Active current (ICC1) <35mA at 85°C
Standby current 250μA (max) at 85°C
Deep power-down: Typical 10μA
Operating temperature range : -40°C ~ 85°C
Publication Release Date : May 29, 2013
- 1 - Revision : A01-003

1 page




W967D6HB pdf
W967D6HB
128Mb Async./Page,Syn./Burst CellularRAM
10.2.16 WE# - Controlled Asynchronous WRITE ................................................................................................. 57
10.2.17 Asynchronous WRITE Using ADV# ......................................................................................................... 58
10.2.18 Burst WRITE Operation-Variable Latency Mode ..................................................................................... 59
10.2.19 Burst WRITE Operation-Fixed Latency Mode.......................................................................................... 60
10.2.20 Burst WRITE at End of Row (Wrap off).................................................................................................... 61
10.2.21 Burst WRITE Row Boundary Crossing .................................................................................................... 62
10.2.22 Burst WRITE Followed by Burst READ.................................................................................................... 63
10.2.23 Burst READ Interrupted by Burst READ or WRITE ................................................................................. 64
10.2.24 Burst WRITE Interrupted by Burst WRITE or READVariable Latency Mode......................................... 65
10.2.25 Burst WRITE Interrupted by Burst WRITE or READ-Fixed Latency Mode .............................................. 66
10.2.26 Asynchronous WRITE Followed by Burst READ ..................................................................................... 67
10.2.27 Asynchronous WRITE (ADV# LOW) Followed by Burst READ ............................................................... 68
10.2.28 Burst READ Followed By Asynchronous WRITE (WE# - Controlled)...................................................... 69
10.2.29 Burst READ Followed By Asynchronous WRITE Using ADV# ................................................................ 70
10.2.30 Asynchronous WRITE Followed by Asynchronous READ - ADV# LOW................................................. 71
10.2.31 Asynchronous WRITE Followed by Asynchronous READ....................................................................... 72
11. PACKAGE DESCRIPTION.................................................................................................... 73
11.1 Package Dimension ........................................................................................................................ 73
12. REVISION HISTORY ............................................................................................................. 74
Publication Release Date : May 29, 2013
- 5 - Revision : A01-003

5 Page





W967D6HB arduino
W967D6HB
128Mb Async./Page,Syn./Burst CellularRAM
8. FUNCTIONAL DESCRIPTION
In general, CellularRAM devices are high-density alternatives to SRAM and Pseudo SRAM products, popular in low-
power, portable applications. The device implements the same high-speed bus interface found on burst mode Flash
products. The CellularRAM bus interface supports both asynchronous and burst mode transfers. Page mode
accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol.
8.1 Power Up Initialization
CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process.
Initialization will configure the BCR and the RCR with their default settings. VCC and VCCQ must be applied
simultaneously. When they reach a stable level at or above 1.7V, the device will require 150μs to complete its self-
initialization process. During the initialization period, CE# should remain HIGH. When initialization is complete, the
device is ready for normal operation.
8.1.1 Power-Up Initialization Timing
Vcc =1.7v
Vcc
VccQ
tpu >=150 us
Device Initialization
Device ready for
normal operation
8.2 Bus Operating Modes
CellularRAM products incorporate a burst mode interface found on flash products targeting low-power, wireless
applications. This bus interface supports asynchronous, page mode, and burst mode read and write transfers. The
specific interface supported is defined by the value loaded into the BCR. Page mode is controlled by the refresh
configuration register (RCR[7]).
8.2.1 Asynchronous Modes
CellularRAM products power up in the asynchronous operating mode. This mode uses the industry- standard SRAM
control bus (CE#, OE#, WE#, LB#/UB#). READ operations are initiated by bringing CE#, OE#, and LB#/UB# LOW
while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified access time has elapsed.
WRITE operations occur when CE#, WE#, and LB#/UB# are driven LOW. During asynchronous WRITE operations,
the OE# level is a ―don't care,‖ and WE# will override OE#. The data to be written is latched on the rising edge of
CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode disabled) can either use the
ADV input to latch the address, or ADV can be driven LOW during the entire READ/WRITE operation.
During asynchronous operation, the CLK input must be held static LOW. WAIT will be driven while the device is
enabled and its state should be ignored. WE# LOW time must be limited to tCEM.
- 11 -
Publication Release Date : May 29, 2013
Revision : A01-003

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet W967D6HB.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
W967D6HBCellularRAMWinbond
Winbond

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar